TMS570LS datasheet(93/107 Pages) TI1

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t(RTP)dsu

t(RTP)

dho

RTPSYNC

RTPCLK

RTPDATA

t(RTP)

sho

t(RTP)ssu

t(RTP)cyc

t(RTP)h

t(RTP)l

TMS570LS20206-EP, TMS570LS20216-EP

www.ti.com

SPNS209A – JUNE 2012 – REVISED AUGUST 2012

7.16 RTP Timings

7.16.1 RTPCLK Timing

Figure 7-21. RTPCLK Timing

Table 7-22. RTPCLK Timing

Parameter

Minimum

Description

t(RTP)cyc

10 ns

Clock period (depending on HCLK divide

ratio)

t(RTP)h

(t(RTP)cyc/2) - ((tr+tf)/2) -1.5

High pulse width (depending on HCLK divide

ratio and load on pin)

t(RTP)l

(t(RTP)cyc/2) - ((tr+tf)/2) -1.5

Low pulse width (depending on HCLK divide

ratio and load on pin)

7.16.2 RTPDATA Timing

Figure 7-22. RTPDATA Timing

Table 7-23. RTPDATA Timing

Parameter

Minimum

Description

t(RTP)dsu

0.5 t(RTP)cyc-3ns

Data setup time

t(RTP)dho

0.5 t(RTP)cyc-2ns

Data hold time

t(RTP)ssu

0.5 t(RTP)cyc-3ns

SYNC setup time

t(RTP)sho

0.5 t(RTP)cyc-2ns

SYNC hold time

Note: The timings in this table are measured with a 50pF and 50µA load. And they are measured at the 50% point, not 20% or 80% point.

Peripheral and Electrical Specifications

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Product Folder Link(s): TMS570LS20206-EP TMS570LS20216-EP

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