TMS570LS datasheet(17/107 Pages) TI1

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TMS570LS20206-EP, TMS570LS20216-EP

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SPNS209A – JUNE 2012 – REVISED AUGUST 2012

2.3.6

PBIST RAM Self Test

The PBIST (Programmable Built-In Self Test) architecture provides a run-time-programmable memory

BIST engine for varying levels of test coverage across the device’s embedded RAM memory. The PBIST

architecture consists of a small CPU with an instruction set targeted specifically towards testing RAM

memories. This CPU includes both control and instruction registers necessary to execute the individual

memory algorithms. In order to minimize test load overhead, once an algorithm is loaded into the

instruction registers, it can be run on multiple memories of different sizes or types. The memory

configuration information and test algorithm code is stored in an on-chip ROM. The PBIST RAM groups

implemented on this device are shown in the following table. More information about memory self test can

be found in the PBIST chapter of the device TRM.

Table 2-8. PBIST RAM Grouping

RAM

Module

Memory Type

RGS

Test Pattern (Algorithm)

Group

/RDS(1)

Triple

March

Down 1A

Pre-

Map

DTXN 2A

PMOS

slow

fast read

13N

[HCLK/

charge

column

[HCLK/

open

read

[ROM

[HCLK/

VCLK(2)

[HCLK/

VCLK(2)

[HCLK/

[ROM

clock

VCLK(2)

cycles]

VCLK(2)

cycles]

VCLK(2)

clock

cycles]

PBIST

ROM

0/1

12290

4098

ROM

STC

ROM

13/1

24578

8194

ROM

DCAN1

1/0..2

12600

2637

2064

1914

5490

11544

DCAN2

2/0..2

12600

2637

2064

1914

5490

11544

DCAN3

3/0..2

6360

1341

1104

1146

2754

5016

ESRAM

SP, multi-strobe

4/21..22

266320

52254

41120

33212

181260

409616

w/page mode

MibSPI

5/0..5

50160

10458

7968

6900

21924

52272

VIM

6/0

4200

879

688

638

1830

3848

MibADC

2P, sync write

7/0..1

8400

1758

1376

1276

3660

7696

async read

DMA

2P, sync write

8/0..5

18960

4410

3072

2772

6084

Not

async read

Available

NHET

2P, sync write

9/0..11

25440

5940

4224

4008

8136

20064

async read

HET TU

2P, sync write

10/0..5

6480

1530

1152

1236

2052

4272

async read

RTP

2P, sync write

11/0..8

37800

8775

6048

5310

12150

34632

async read

FlexRay

12/0..7

175040

34872

27296

22608

108912

246336

ESRAM

SP, multi-strobe

4/20

133160

26127

20560

16606

90630

204808

w/ page mode

SP = Single Port RAM; 2P = Two Port RAM

(1)

RGS (RAM group select) and RDS (return data select) stand for an unique RAM select id. More information about the RGS and the

RDS can be found in the technical reference manual (TRM)

(2)

The test clock for ESRAM, DMA and RTP is HCLK; the test clock for other modules is VCLK.

NOTE

•

The March13N test algorithm is recommended for application testing.

•

The maximum PBIST test execution speed is limited to 100MHz.

•

The supply current while performing PBIST self test is different than the device operating

mode current. These values can be found in the Icc section of the device electrical

specifications.

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