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TMS570LS bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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TMS570LS bảng dữ liệu(HTML) 1 Page - Texas Instruments |
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1 / 107 page ![]() TMS570LS20206-EP, TMS570LS20216-EP www.ti.com SPNS209A – JUNE 2012 – REVISED AUGUST 2012 TMS570LS Series 16/32-BIT RISC Flash Microcontroller Check for Samples: TMS570LS20206-EP, TMS570LS20216-EP 1 TMS570LS Series 16/32-BIT RISC Flash Microcontroller 1.1 Features 1 • The TMS570LS20206-EP and TMS570LS20216- • Frequency-Modulated Zero-Pin Phase-Locked EP use the same silicon (die) as the TMS Loop (FMzPLL)-Based Clock Module TMS570LS Series IEC 61508 SIL3 certified – Oscillator and PLL clock monitor microcontroller family however it is instead • Up to 115 Peripheral IO pins certified to meet GEIA-STD-00021-1 for – 16 Dedicated GIO - 8 w/ External Interrupts Aerospace Qualified Electronic Components – Programmable External Clock (ECLK) and tested for operation over the military • Communication Interfaces temperature range. – Three Multi-buffered Serial Peripheral • High-Performance Microcontroller Interface (MibSPI) each with: – Dual CPUs running in Lockstep • Four Chip Selects and one Enable pin – ECC on Flash and SRAM • 128 buffers with parity – CPU and Memory BIST (Built-In Self Test) • One with parallel mode – Error Signaling Module (ESM) w/ Error Pin – Two UART (SCI) interfaces with Local • ARM® Cortex™-R4F 32-Bit RISC CPU Interconnect Network Interface (LIN 2.0) – Efficient 1.6 DMIPS/MHz with 8-stage – Three CAN (DCAN) Controller pipeline • Two with 64 mailboxes, one with 32 – Floating Point Unit with Single/Double • Parity on mailbox RAM Precision – Dual Channel FlexRay™ Controller – Memory Protection Unit (MPU) • 8K-Byte message RAM with parity – Open Architecture With Third-Party Support • Transfer Unit with MPU and parity • Operating Features • High-End Timer (NHET) – Up to 160-MHz System Clock – 32 Programmable I/O Channels – Core Supply Voltage (VCC): 1.5 V – 128 Words High-End Timer RAM with parity – I/O Supply Voltage (VCCIO): 3.3 V – Transfer Unit with MPU and parity • Integrated Memory • Two 12-Bit Multi-Buffered ADCs (MibADC) – 2M-Byte Flash with ECC – 24 total ADC Input channels – 60K-Byte RAM with ECC – Each has 64 Buffers with parity • Multiple Communication interfaces including • Trace and Calibration Interfaces FlexRay, CAN, and LIN – Embedded Trace Module (ETMR4) • NHET Timer and 2x 12-bit ADCs – Data Modification Module (DMM) • External Memory Interface (EMIF) – RAM Trace Port (RTP) – 16bit Data, 22bit Address, 4 Chip Selects – Parameter Overlay Module (POM) • Common TMS570 Platform Architecture • On-Chip emulation logic including IEEE 1149.1 – Consistent Memory Map across the family JTAG, Boundary Scan and ARM Coresight – Real-Time Interrupt (RTI) OS Timer components – Vectored Interrupt Module (VIM) • Full Development Kit Available – Cyclic Redundancy Checker (CRC, – Development Boards 2 Channels) – Code Composer Studio Integrated • Direct Memory Access (DMA) Controller Development Environment (IDE) – 32 DMA requests and 16 Channels/ Control – HaLCoGen Code Generation Tool Packets – HET Assembler and Simulator – Parity on Control Packet Memory – nowFlash Flash Programming Tool – Dedicated Memory Protection Unit (MPU) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to Copyright © 2012, Texas Instruments Incorporated specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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