TMS570LS datasheet(63/107 Pages) TI1

63 / 107 page

TMS570LS20206-EP, TMS570LS20216-EP

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SPNS209A – JUNE 2012 – REVISED AUGUST 2012

6.4

Thermal Information

TMS570LS20206

TMS570LS20216

THERMAL METRIC

UNITS

GWT

PGE

337 BALL

144 PINS

θJA

Junction-to-ambient thermal resistance(1)

30.7

32.1

θJCtop

Junction-to-case (top) thermal resistance(2)

4.7

3.3

θJB

Junction-to-board thermal resistance(3)

13.7

°C/W

ψJT

Junction-to-top characterization parameter(4)

0.1

ψJB

Junction-to-board characterization parameter(5)

13.3

θJCbot

Junction-to-case (bottom) thermal resistance(6)

N/A

(1)

The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2)

The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3)

The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4)

The junction-to-top characterization parameter,

ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5)

The junction-to-board characterization parameter,

ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining

θJA , using a procedure described in JESD51-2a (sections 6 and 7).

(6)

The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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