TMS570LS datasheet(71/107 Pages) TI1

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Address Waitstates

Data Waitstates

RAM

Address Waitstates

Data Waitstates

Flash

0MHz

f(HCLK)

100MHz

108MHz

72MHz

36MHz

TMS570LS20206-EP, TMS570LS20216-EP

www.ti.com

SPNS209A – JUNE 2012 – REVISED AUGUST 2012

7.1.5

Switching Characteristics Over Recommended Operating Conditions For Clocks

Table 7-4. Switching Characteristics Over Recommended Operating Conditions For Clocks

Parameter

Test Conditions

MIN

MAX

Unit

f(HCLK)

HCLK - System clock frequency (337 BGA

Pipeline mode enabled

160

MHz

packages)

Pipeline mode disabled

MHz

f(HCLK)

HCLK - System clock frequency (144pin QFP

Pipeline mode enabled

140

MHz

package)

Pipeline mode disabled

MHz

f(GCLK)

GCLK - CPU clock frequency (ratio GCLK :

f(HCLK)

MHz

HCLK = 1:1)

f(RCLK)

RCLK - Frequency out of PLL macro into R-

160

MHz

divider

f(RTICLK)

(1)

RTICLK - clock frequency

f(VCLK)

MHz

f(VCLK)

VCLK - Primary peripheral clock frequency

f(VCLK2)

MHz

f(VCLK2)

VCLK2 - Secondary peripheral clock frequency

100

MHz

f(AVCLK1)

AVCLK1 - Primary asynchronous peripheral clock

f(VCLK)

MHz

frequency

f(AVCLK2)

AVCLK2 - Secondary asynchronous peripheral

f(VCLK)

MHz

clock frequency

f(ECLK)

(2)

ECLK - External clock output frequency for ECP

MHz

Module

f(PROG/ERASE)

System clock frequency - Flash

f(HCLK)

MHz

programming/erase

(1)

If the RTIx clock source is chosen to be anything other than the default VCLK, then the RTI clock needs to be at least three times slower

than the VCLK.

(2)

(ECLK) = f(VCLK) / N, where N = {1 to 65536}. N is the ECP prescale value defined by the ECPCNTL.[15:0] register bits in the System

module. Pipeline mode enabled or disabled is determined by the FRDCNTL[2:0].

7.1.5.1

Timing - Wait States

Figure 7-3. Wait States

NOTE

If FMzPLL frequency modulation is enabled, special care must be taken to ensure that the

maximum system clock frequency f(HCLK) and peripheral clock frequency f(VCLK) are not

exceeded. The speed of the device clocks may need be derated to accommodate the

modulation depth when FMzPLL frequency modulation is enabled.

Peripheral and Electrical Specifications

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