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TMS570LS bảng dữ liệu(PDF) 49 Page - Texas Instruments

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TMS570LS bảng dữ liệu(HTML) 49 Page - Texas Instruments

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TMS570LS20206-EP, TMS570LS20216-EP
www.ti.com
SPNS209A – JUNE 2012 – REVISED AUGUST 2012
4.6
MIBSPI
4.6.1
MIBSPI Event Trigger Sources
The Multi-buffered Serial Peripheral Interfaces (MIBSPIs) have a programmable buffer memory that
enables data transmission to be completed without CPU intervention. The buffers are combined in
different Transfer Groups (TGs) that can be triggered by external events such as I/O activity, timers or by
the internal tick counter. The internal tick counter supports the periodic trigger of events. Each buffer of the
MibSPI can be associated with different DMA channels in different TGs, allowing the user to move data
between internal memory and an external slave with minimal CPU interaction.
Table 4-8. MIBSPI1 Event Trigger Sources
Event
TGxCTRL TRIGSRC[3:0]
Hookup
Disabled
0000
No trigger source
EVENT0
0001
GIOA[0]
EVENT1
0010
GIOA[1]
EVENT2
0011
GIOA[2]
EVENT3
0100
GIOA[3]
EVENT4
0101
GIOA[4]
EVENT5
0110
GIOA[5]
EVENT6
0111
GIOA[6]
EVENT7
1000
GIOA[7]
EVENT8
1001
NHET[8]
EVENT9
1010
NHET[10]
EVENT10
1011
NHET[12]
EVENT11
1100
NHET[14]
EVENT12
1101
NHET[16]
EVENT13
1110
NHET[18]
EVENT14
1111
Internal Tick counter
Table 4-9. MIBSPI3 Event Trigger Sources
Event
TGxCTRL TRIGSRC[3:0]
Hookup
Disabled
0000
No trigger source
EVENT0
0001
GIOA[0]
EVENT1
0010
GIOA[1]
EVENT2
0011
GIOA[2]
EVENT3
0100
GIOA[3]
EVENT4
0101
GIOA[4]
EVENT5
0110
GIOA[5]
EVENT6
0111
GIOA[6]
EVENT7
1000
GIOA[7]
EVENT8
1001
NHET[8]
EVENT9
1010
NHET[10]
EVENT10
1011
NHET[12]
EVENT11
1100
NHET[14]
EVENT12
1101
NHET[16]
EVENT13
1110
NHET[18]
EVENT14
1111
Internal Tick counter
Copyright © 2012, Texas Instruments Incorporated
Peripherals
49
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Product Folder Link(s): TMS570LS20206-EP TMS570LS20216-EP



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