TMS570LS datasheet(73/107 Pages) TI1

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3.3 V

1.5 V

CCIOPORL

PORRST

VCC (1.5 V)

VCCPORH

VIL(PORRST)

VCCIOPORH

VCCIOPORL

VCCPORL

VCC

VCCIO / VCCP

VCCPORH

VCCPORL

VIL

VIL(PORRST)

TMS570LS20206-EP, TMS570LS20216-EP

www.ti.com

SPNS209A – JUNE 2012 – REVISED AUGUST 2012

7.3

RST And PORRST Timings

7.3.1

Timing Requirements For PORRST

Table 7-6. Timing Requirements For PORRST

NO.

MIN

MAX

Unit

VCCPORL

(1)

VCC low supply level when PORRST must be active during power up

0.5

VCCPORH

(1)

VCC high supply level when PORRST must remain active during power up

1.35

and become active during power down

VCCIOPORL

(1)

VCCIO / VCCP low supply level when PORRST must be active during

1.1

power up

VCCIOPORH

(1)

VCCIO / VCCP high supply level when PORRST must remain active during

power up and become active during power down

VIL(PORRST)

(1)

Low-level input voltage of PORRST VCCIO > 2.5V

0.2 VCCIO

Low-level input voltage of PORRST VCCIO< 2.5V

0.5

tsu(PORRST)

(1)

Setup time, PORRST active before VCCIO and VCCP > VCCIOPORL during

power up

th(PORRST)

(1)

Hold time, PORRST active after VCC > VCCPORH

tsu(PORRST)

(1)

Setup time, PORRST active before VCC <= VCCPORH during power down

µs

th(PORRST)

(1)

Hold time, PORRST active after VCCIO and VCCP > VCCIOPORH

th(PORRST)

(1)

Hold time, PORRST active after VCC < VCCPORL

tf(PORRST)

(1)

Filter time PORRST, pulses less than MIN will be filtered out, pulses

150

greater than MAX are guaranteed to generate a reset(2)

tf(RST)

Filter time RST, pulses less than MIN will be filtered out, pulses greater

150

than MAX are guaranteed to generate a reset

(1)

This parameter is characterized from -40°C to 125°C only.

(2)

A low pulse on the nPORRST pin which is just barely longer than the glitch filter implemented on this pin will result in a very short

internal reset. This may result in unpredictable behavior as some parts of the device may be reset while other parts of the device are

not.

Figure 7-5. PORRST Timing Diagram

NOTE

There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage;

this is just an exemplary drawing. All requirements are to ensure PORRST is active when

VCCIO or VCC is out of the normal operating range.

Peripheral and Electrical Specifications

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