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SPC574K72E5 bảng dữ liệu(PDF) 101 Page - STMicroelectronics

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SPC574Kxx
Electrical characteristics
126
Figure 36. DSPI LVDS and CMOS master timing – output only – modified transfer
format MTFE = 1, CHPA = 1
3.17.2.2
Slave Mode timing
2.
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
3.
All timing values for output signals in this table are measured to 50% of the output voltage.
4.
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
5.
With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.
6.
tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
7.
SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
PCSx
SCK Output
SOUT
First Data
Data
Last Data
(CPOL = 0)
tSUO
tHO
tCSV
tSDC
tSCK
tCSH
Table 53. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)(1)
#
Symbol
C
Characteristic
Condition
Min
Max
Unit
Pad Drive
Load
1tSCK
CC
D
SCK Cycle Time(2)
—
—
62
—ns
2tCSC
SR
D
SS to SCK Delay(2)
—
—
16
—ns
3tASC
SR
D
SCK to SS Delay(2)
—
—
16
—ns
4tSDC
D
SCK Duty Cycle(2)
—
—30
—
ns
5tA
CC
D
Slave Access Time(2),(3),(4)
(SS active to SOUT driven)
Very
Strong
25 pF
—
50
ns
Strong
50 pF
—
50
ns
Medium
50 pF
—
60
ns
6tDIS
CC
D
Slave SOUT Disable
Time(2),(3),(4)
(SS inactive to SOUT High-Z
or invalid)
Very
Strong
25 pF
—
5ns
Strong
50 pF
—
5ns
Medium
50 pF
—
10
ns



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