MT9075B datasheet(62/78 Pages) MITEL

62 / 78 page

MT9075B

Preliminary Information

Table 95 - HDLC Test Control Register

(Pages 0BH & 0CH, Address 1BH) (continued)

Bit

Name

Functional Description

7 - 0

Crc7 - 0

The LSB byte of the CRC received

from the transmitter. These bits are

as the transmitter sent them; that is,

most

significant

bit

first

and

inverted. This register is updated at

the end of each received packet and

therefore should be read when end

of packet is detected.

Table 93 - Receive CRC LSB Register

(Pages 0BH & 0CH, Address 19H)

Bit

Name

Functional Description

7 - 0

Cnt7 - 0

(0000

0000)

The

Transmit

Byte

Count

length of the packet about to be

transmitted.

When

this

reaches the count of one, the next

write to the Tx FIFO will be tagged

as an end of packet byte. The

counter decrements at the end of

the write to the Tx FIFO. If the Cycle

bit of Control Register 2 is set high,

the counter will cycle through the

programmed value continuously.

Table 94 - Transmit Byte Count register

(Pages B & C, Address 1AH)

Bit

Name

Functional Description

HRST

(0000

0000)

HDLC Reset. When this bit is set to

one, the HDLC will be reset. This is

similar to RESET being applied, the

only difference being that this bit will

not be reset automatically. This bit

can only be reset by writing a zero

twice to this location or applying

RESET.

Bit

Name

Functional Description

RTloop

(0)

RT Loopback. When this bit is set

to one, receive to transmit HDLC

loopback will be activated. Receive

data,

including

end

packet

indication, but not including flags or

CRC, will be written to the TX FIFO

as well as the RX FIFO. When the

transmitter is enabled, this data will

be transmitted as though written by

the microprocessor. Both good and

bad packets will be looped back.

Receive to transmit loopback may

also be accomplished by reading

the

FIFO

using

the

microprocessor and writing these

bytes, with appropriate tags, into the

TX FIFO.

RSV

(0)

Reserved; must be set to 0 for

normal operation.

RSV

(0)

Reserved; must be set to 0 for

normal operation.

RSV

(0)

Reserved; must be set to 0 for

normal operation.

Ftst

(0)

FIFO Test. This bit when set to one

allows the writing to the RX FIFO

and reading of the TX FIFO through

the microprocessor to allow more

efficient testing of the FIFO status/

interrupt functionality. This is done

by making a TX FIFO write become

a RX FIFO write and a RX FIFO

read become a TX FIFO read. In

addition, EOP/FA and RQ8/RQ9 are

re-defined to be accessible (i.e. RX

write causes EOP/FA to go to RX

fifo input; TX read looks at output of

TX FIFO through RQ8/RQ9 bits).

RSV

(0)

Reserved; must be set to 0 for

normal operation.

---

Unused.

Table 95 - HDLC Test Control Register

(Pages 0BH & 0CH, Address 1BH)

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