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MT9075B bảng dữ liệu(PDF) 11 Page - Mitel Networks Corporation |
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MT9075B bảng dữ liệu(HTML) 11 Page - Mitel Networks Corporation |
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11 / 78 page ![]() Preliminary Information MT9075B 11 Depending on the mode selected, the Jitter Attenuator (JA) can attenuate either transmit clock jitter or receive clock jitter, or be disconnected. Control bits JAS, JAT/JAR (address 18H of page 02H) determine the JA selection under certain modes. Table 2 shows the configuration of related control pins and control bits required to place the MT9075B in the appropriate jitter attenuation mode. Referring to the mode names given in Table 2, the basic operation of the jitter attenuation modes is summarized as follows: •In SysBusSync (1-3) modes, pins C4b and F0b are always configured as inputs, while in the Line Synchronous and Free-Run modes C4b and F0b are configured as outputs. •In SysBusSync1 mode, an external clock is applied to C4b. The applied clock is dejittered by the internal PLL before being used to transmit data. The clock extracted (with no jitter attenuation performed) from the receive data can be monitored on pin E2o. •In SysBusSync2 mode, the clock applied to pin C4b is assumed to be jitter-free and is directly used to transmit data. The internal PLL is used to dejitter the extracted receive clock. The dejittered receive clock is output on pin E2o. •In SysBusSync3 mode, no jitter attenuation is applied to either the transmit or receive clocks. The transmit data is synchronized to clock applied to pin C4b. The extracted receive clock is not dejittered and is supplied directly to the E2o output. •In Line Synchronous mode, the clock extracted from the receive data is dejittered using the internal PLL and then output on pin C4b. Pin E2o provides the extracted receive clock before it has been dejittered. The transmit data is synchronous to the clean receive clock. •In Free-Run mode the transmit data is synchronized to the internally generated clock. The internal clock is output on pin C4b. The clock signal extracted from the receive data is not dejittered and is output directly on pin E2o. The PCM 30 Interface PCM 30 (E1) basic frames are 256 bits long and are transmitted at a frame repetition rate of 8000 Hz, which results in an aggregate bit rate of 256 bits x 8000/sec = 2.048 Mbits/sec. The actual bit rate is 2.048 Mbits/sec +/-50 ppm encoded in HDB3 format. The HDB3 control bit (page 01H, address 15H, bit 5) selects either HDB3 encoding or alternate mark inversion (AMI) encoding. Basic frames are divided into 32 time slots numbered 0 to 31, see Figure 31. Each time slot is 8 bits in length and is transmitted most significant bit first (numbered bit 1). This results in a single time slot data rate of 8 bits x 8000/sec. = 64 kbits/sec. It should be noted that the Mitel ST-BUS also has 32 channels numbered 0 to 31, but the most significant bit of an eight bit channel is numbered bit 7 (see Mitel Application Note MSAN-126). Therefore, ST- BUS bit 7 is synonymous with PCM 30 bit 1; bit 6 with bit 2: and so on (Figure 31). PCM 30 time slot 0 is reserved for basic frame alignment, CRC-4 multiframe alignment and the communication of maintenance information. In most configurations time slot 16 is reserved for either Channel Associated Signalling (CAS or ABCD bit signalling) or Common Channel Signalling (CCS). The remaining 30 time slots are called channels and carry either PCM encoded voice signals or digital Table 2 - Selection of Clock Jitter Attenuation Modes Mode Name BS/LS BL/FR JAS JAT/JAR Note SysBusSync1 1 1 1 1 JA on Tx side; No JA on Rx side SysBusSync2 1 1 1 0 JA on Rx side; No JA on Tx side SysBusSync3 1 1 0 x No JA on Tx or Rx side Line Synchronous 0 1 x x By default, JA is on the receive side. Controls bits need not be selected. Free-Run x 0 x x In free-run mode JA will be automatically disconnected |
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