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MT9075B bảng dữ liệu(PDF) 15 Page - Mitel Networks Corporation

tên linh kiện MT9075B
Giải thích chi tiết về linh kiện  E1 Single Chip Transceiver
PDF  78 Pages
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nhà sản xuất  MITEL [Mitel Networks Corporation]
Trang chủ  http://www.mitel.com
Logo MITEL - Mitel Networks Corporation

MT9075B bảng dữ liệu(HTML) 15 Page - Mitel Networks Corporation

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Preliminary Information
MT9075B
15
used to control the transmit channel associated
signalling. The DSTi and DSTo streams contain the
transmit and receive voice and digital data.
Identification Code
The MT9075B shall be identified by the code
10101010, read from the identification code status
register (page 03H, address 1FH).
Reset Operation (Initialization)
The MT9075B can be reset using the hardware
RESET pin (pin 11 in PLCC, pin 84 in MQFP, see pin
description for external reset circuit requirements) or
the software reset bit RST (page 01H, address 11H).
When the device emerges from its reset state it will
begin to function with the default settings described
in Table 6. A reset operation takes 1 full frame (125
us) to complete.
Table 6 - Reset Status
Transmit AIS Operation
The pin TAIS (Transmit AIS, pin 60 in PLCC, pin 48 in
MQFP) allows an all ones signal to be transmitted
from the point of power-up without the need to write
any control registers. During this time the IRQ pin is
tristated. After the interface has been initialized
normal operation can take place by making TAIS
high.
National Bit Buffers
Table 7 shows the contents of the transmit and
receive Frame Alignment Signals (FAS) and Non-
frame Alignment Signals (NFAS) of time slot zero of
a PCM 30 signal. Even numbered frames (CRC
Frame # 0, 2, 4,...) are FASs and odd numbered
frames (CRC Frame # 1, 3, 5,...) are NFASs. The bits
of each channel are numbered 1 to 8, with bit 1 being
the most significant and bit 8 the least significant.
Table 7 - FAS and NFAS Structure
Table 8 illustrates the organization of the MT9075B
transmit and receive national bit buffers. Each row is
an addressable byte of the MT9075B national bit
buffer, and each column contains the national bits of
an odd numbered frame of each CRC-4 Multiframe.
The transmit and receive national bit buffers are
located at page 0DH and 0EH respectively.
Function
Status
Mode
Termination
Loopbacks
Deactivated
Transmit FAS
Cn0011011
Transmit non-FAS
1/Sn1111111
Transmit MFAS (CAS)
00001111
Data Link
Deactivated
CRC Interworking
Activated
Signalling
CAS Registers
ABCD Bit Debounce
Deactivated
Interrupts
Interrupt Mask Word
Zero unmasked, all
others masked;
interrupts not suspended
RxMF Output
Signalling Multiframe
Error Insertion
Deactivated
HDLCs
Deactivated
Counters
Cleared
Tx Message Buffer
All locations set to 54H
Per Time Slot Control
Buffer
All locations cleared
CRC
CRC
Frame/
Type
PCM 30 Channel Zero
12
3
4
5678
0/FAS
C1
0
0
11011
1/NFAS
01A
Sa4 Sa5 Sa6 Sa7 Sa8
2/FAS
C2
0
0
11011
3/NFAS
01A
Sa4 Sa5 Sa6 Sa7 Sa8
4/FAS
C3
0
0
11011
5/NFAS
11A
Sa4 Sa5 Sa6 Sa7 Sa8
6/FAS
C4
0
0
11011
7/NFAS
01A
Sa4 Sa5 Sa6 Sa7 Sa8
8/FAS
C1
0
0
11011
9/NFAS
11A
Sa4 Sa5 Sa6 Sa7 Sa8
10/FAS
C2
0
0
11011
11/NFAS
11A
Sa4 Sa5 Sa6 Sa7 Sa8
12/FAS
C3
0
0
11011
13/NFAS
E1
1A
Sa4 Sa5 Sa6 Sa7 Sa8
14/FAS
C4
0
0
11011
15/NFAS
E2
1A
Sa4 Sa5 Sa6 Sa7 Sa8
indicates position of CRC-4 multiframe alignment signa



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