MT9075B datasheet(60/78 Pages) MITEL

60 / 78 page

MT9075B

Preliminary Information

Table 88 - HDLC Status Register

(Pages 0BH & 0CH, Address 14H)

Bit

Name

Functional Description

3, 2

Txstat2,

Txstat1

Transmit

Status.

These

bits

indicate the status of the TX FIFO

as follows:

Txsta

TX FIFO Status

TX FIFO full up to

the selected status

level or more. See

Table 93.

The number of bytes

in the TX FIFO has

reached

exceeded

the

selected

interrupt

threshold level. See

Table 94.

TX FIFO empty.

The number of bytes

in the TX FIFO is

less

than

the

selected

interrupt

threshold level. See

Table 94.

1, 0

Rxstat2,

Rxstat1

Receive

Status.

These

bits

indicate the status of the RX FIFO

as follows:

Rxsta

RX FIFO Status

RX FIFO empty.

The number of bytes

in the RX FIFO is

less

than

the

selected

threshold

level. See Table 94.

RX FIFO full up to

the selected status

level or more. See

Table 93.

The number of bytes

in the RX FIFO has

reached

exceeded

the

selected

interrupt

threshold level. See

Table 94.

Bit

Name

Functional Description

Intsel

(0)

Interrupt Selection. When one, this

bit will cause bit 2 of the Interrupt

underrun (TXunder). When zero,

this interrupt will reflect a frame

abort (FA).

Cycle

(0)

When one, this bit will cause the

transmit byte count to cycle through

the value loaded into the Transmit

Byte Count Register.

Tcrci

(0)

Transmit CRC Inhibited. When

one, this bit will inhibit transmission

of the CRC. That is, the transmitter

will not insert the computed CRC

onto the bit stream after seeing the

EOP tag byte. This is used in V.120

terminal adaptation for synchronous

protocol sensitive UI frames.

Seven

(0)

Seven Bits Address Recognition.

When one, this bit will enable seven

bits of address recognition in the

first address byte. The received

address byte must have bit 0 equal

which

indicates

single

address byte is being received.

RSV

(0)

Reserved, must be zero for normal

operation.

RSV

(0)

Reserved, must be zero for normal

operation.

Rxfrst

(0)

RX FIFO Reset. When one, the RX

FIFO will be reset. This causes the

receiver to be disabled until the next

reception of a flag. The status

being empty. However, the actual

bit values in the RX FIFO will not be

reset.

Txfrst

(0)

TX FIFO Reset. When one, the TX

FIFO will be reset. The Status

being empty. This bit will be reset

when data is written to the TX FIFO.

However, the actual bit values of

data in the TX FIFO will not be

reset. It is cleared by the next write

to the TX FIFO.

Table 89 - HDLC Control Register 2

(Pages 0BH & 0CH, Address 15H)

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