MT9075B datasheet(58/78 Pages) MITEL

58 / 78 page

MT9075B

Preliminary Information

Table 83 - HDLC Address Recognition Register1

(Page 0BH & 0CH, Address 10H)

Bit

Name

Functional Description

7 - 2

Adr16

Adr11

(000000)

A six bit mask used to interrogate

the

first

byte

the

received

address. Adr16 is the MSB.

Adr10

(0)

This

bit

used

address

comparison, if control bit Seven, bit

4 of HDLC Control Register 2

(address 15H) is one.

A1en

(0)

When this bit is high, this six (or

seven) bit mask is used in address

comparison of the first address

byte.

If address recognition is enabled,

any

packet

failing

the

address

comparison will not be stored in the

RX FIFO. A1en must be high for All-

call (1111111) address recognition

for single byte address. When this

bit is low, this bit mask is ignored in

address comparison

Bit

Name

Functional Description

7 - 1

Ad26

Ad20

(000000)

seven

bit

mask

used

interrogate the second byte of the

received address. Adr26 is MSB.

This mask is ignored (as well as first

byte

mask)

all

call

address

(1111111) is received.

A2en

(0)

When this bit is one, this seven bit

mask

used

address

comparison of the second address

byte.

If address recognition is enabled,

any

packet

failing

the

address

comparison will not be stored in the

Rx FIFO. A2en must be one for All-

call address recognition. When this

bit is zero, this bit mask is ignored in

address comparison

Table 84 - HDLC Address Recognition Register 2

(Pages 0BH & 0CH, Address 11H)

Bit

Name

Functional Description

7 - 0

Bit7

Bit0

This eight bit word is tagged with

the two status bits (EOP and FA)

from the Control Register 1, and the

resulting 10 bit word is written to the

TX FIFO. The FIFO status is not

changed immediately after a write

or read occurs. It is updated after

the data and the read/write pointers

have settled.

Table 85 - TX FIFO Write Register

(Pages 0BH & 0CH, Address 12H)

Bit

Name

Functional Description

7 - 0

Bit7

Bit0

This is the received data byte read

from the RX FIFO. The status bits of

this byte can be read from the

status register. The FIFO status is

not changed immediately when a

write or read occurs. It is updated

after the data and the read/write

pointers have settled.

Table 86 - RX FIFO Read Register

(Pages 0BH & 0CH, Address 12H)

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