MT9075B datasheet(24/78 Pages) MITEL

24 / 78 page

MT9075B

Preliminary Information

Loopbacks

In order to meet PRI Layer 1 requirements and to

assist in circuit fault sectionalization, the MT9075B

has six loopback functions. The control bits for

digital,

remote,

ST-BUS,

payload

and

metallic

loopbacks are located on page 01H, address 15H.

The remote and local time slot loopbacks are

controlled through control bits 5 and 4 of the Per

Time Slot Control Words on pages 07H and 08H.

Digital Loopback (DG Loop) - DSTi to DSTo at the

framer LIU interface. Bit DLBK = 0 normal; DLBK = 1

activate.

Remote Loopback (RM Loop) - RTIP and RRING

to TTIP and TRING respectively at the PCM 30 side.

Bit RLBK = 0 normal; RLBK = 1 activate.

ST-BUS Loopback (ST Loop) - DSTi to DSTo at

the system side. Bit SLBK = 0 normal; SLBK = 1

activate.

Payload Loopback (PL Loop) - RTIP and RRING

to TTIP and TRING respectively at the system side

with FAS and NFAS operating normally. Bit PLBK = 0

normal; PLBK = 1 activate. The payload loopback is

effectively a physical connection of DSTo to DSTi

within the MT9075B. Channel zero and the DL

originate at the point of loopback.

Metallic Loopback (MT Loop) - The external

signals RTIP and RRING are isolated from the

receiver and the analog outputs TTIP and TRING are

internally connected to the receiver analog input. Bit

MLBK = 0 normal; MLBK = 1 activate.

Local and Remote Time Slot Loopback. Remote

time slot loopback control bit RTSL = 0 normal; RTSL

= 1 activate, will loop around receive PCM 30 time

slots to the transmit PCM 30 time slots. Local time

slot loopback bit LTSL = 0 normal; LTSL = 1 activate,

will loop around DSTi time slots towards the DSTo

time slots.

Error Counters

The MT9075B has nine error counters, which can be

used for maintenance testing, an ongoing measure

of the quality of a PCM 30 link and to assist the

designer in meeting speciﬁcations such as ITU-T

I.431 and G.821. All counters can be preset or

cleared by writing to the appropriate locations. A

separate status page - “1 Second Status” on page

09H - latches the states of the following counters: E-

bit Error Counter, Errored Frame Alignment Signal

Counter, Bipolar Violation Counter and CRC Error

Counter on a one second interval, coincident with

the one second status bit.

Associated with each counter is a maskable event

occurrence

interrupt

and

maskable

counter

overﬂow interrupt. Overﬂow interrupts are useful

when cumulative error counts are being recorded.

For example, every time the frame error counter

overﬂow (FERO) interrupt occurs, 256 frame errors

have been received since the last FERO interrupt. All

counters are cleared and held low by programming

the counter clear bit (master control page 01H,

address 1AH, bit 2) high. Counter overﬂows set bits

in the counter overﬂow latch (page 04H, address

16H); this latch is cleared when read.

The overﬂow reporting latch (page 04H, address

16H) contains a register whose bits are set when

MT9075B

DSTi

DSTo

System

PCM30

MT9075B

DSTo

System

PCM30

MT9075B

DSTi

DSTo

System

PCM30

MT9075B

DSTi

DSTo

System

PCM30

MT9075B

DSTi

DSTo

System

PCM30

MT9075B

DSTi

DSTo

System

PCM30

MT9075B bảng dữ liệu(PDF) 24 Page - Mitel Networks Corporation

MT9075B bảng dữ liệu(HTML) 24 Page - Mitel Networks Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

bảng dữ liệu tải về

Link URL