MC9S08DZ96F2CLL datasheet(150/458 Pages) FREESCALE

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Chapter 7 Central Processor Unit (S08CPUV5)

MC9S08DZ128 Series Data Sheet, Rev. 1

150

Freescale Semiconductor

3. Fetch the high-order half of the interrupt vector.

4. Fetch the low-order half of the interrupt vector.

5. Delay for one free bus cycle.

6. Fetch three bytes of program information starting at the address indicated by the interrupt vector

to ﬁll the instruction queue in preparation for execution of the ﬁrst instruction in the interrupt

service routine.

After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts

while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the

interrupt service routine, this would allow nesting of interrupts (which is not recommended because it

leads to programs that are difﬁcult to debug and maintain).

For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index register pair (H)

is not saved on the stack as part of the interrupt sequence. The user must use a PSHH instruction at the

beginning of the service routine to save H and then use a PULH instruction just before the RTI that ends

the interrupt service routine. It is not necessary to save H if you are certain that the interrupt service routine

does not use any instructions or auto-increment addressing modes that might change the value of H.

The software interrupt (SWI) instruction is like a hardware interrupt except that it is not masked by the

global I bit in the CCR and it is associated with an instruction opcode within the program so it is not

asynchronous to program execution.

7.4.3

Wait Mode Operation

The WAIT instruction enables interrupts by clearing the I bit in the CCR. It then halts the clocks to the

CPU to reduce overall power consumption while the CPU is waiting for the interrupt or reset event that

will wake the CPU from wait mode. When an interrupt or reset event occurs, the CPU clocks will resume

and the interrupt or reset event will be processed normally.

If a serial BACKGROUND command is issued to the MCU through the background debug interface while

the CPU is in wait mode, CPU clocks will resume and the CPU will enter active background mode where

other serial background commands can be processed. This ensures that a host development system can still

gain access to a target MCU even if it is in wait mode.

7.4.4

Stop Mode Operation

Usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to

minimize power consumption. In such systems, external circuitry is needed to control the time spent in

stop mode and to issue a signal to wake up the target MCU when it is time to resume processing. Unlike

the earlier M68HC05 and M68HC08 MCUs, the HCS08 can be conﬁgured to keep a minimum set of

clocks running in stop mode. This optionally allows an internal periodic signal to wake the target MCU

from stop mode.

When a host debug system is connected to the background debug pin (BKGD) and the ENBDM control

bit has been set by a serial command through the background interface (or because the MCU was reset into

active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this

case, if a serial BACKGROUND command is issued to the MCU through the background debug interface

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