MC9S08DZ96F2CLL datasheet(146/458 Pages) FREESCALE

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Chapter 7 Central Processor Unit (S08CPUV5)

MC9S08DZ128 Series Data Sheet, Rev. 1

146

Freescale Semiconductor

Figure 7-2. Condition Code Register

Table 7-1. CCR Register Field Descriptions

Field

Description

Two’s Complement Overﬂow Flag — The CPU sets the overﬂow ﬂag when a two’s complement overﬂow occurs.

The signed branch instructions BGT, BGE, BLE, and BLT use the overﬂow ﬂag.

0 No overﬂow

1 Overﬂow

Half-Carry Flag — The CPU sets the half-carry ﬂag when a carry occurs between accumulator bits 3 and 4 during

an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry ﬂag is required for binary-coded

decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C condition code bits to

automatically add a correction value to the result from a previous ADD or ADC on BCD operands to correct the

result to a valid BCD value.

0 No carry between bits 3 and 4

1 Carry between bits 3 and 4

Interrupt Mask Bit — When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts

are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set

automatically after the CPU registers are saved on the stack, but before the ﬁrst instruction of the interrupt service

routine is executed.

Interrupts are not recognized at the instruction boundary after any instruction that clears I (CLI or TAP). This

ensures that the next instruction after a CLI or TAP will always be executed without the possibility of an intervening

interrupt, provided I was set.

0 Interrupts enabled

1 Interrupts disabled

Negative Flag — The CPU sets the negative ﬂag when an arithmetic operation, logic operation, or data

manipulation produces a negative result, setting bit 7 of the result. Simply loading or storing an 8-bit or 16-bit value

causes N to be set if the most signiﬁcant bit of the loaded or stored value was 1.

0 Non-negative result

1 Negative result

Zero Flag — The CPU sets the zero ﬂag when an arithmetic operation, logic operation, or data manipulation

produces a result of 0x00 or 0x0000. Simply loading or storing an 8-bit or 16-bit value causes Z to be set if the

loaded or stored value was all 0s.

0 Non-zero result

1 Zero result

Carry/Borrow Flag — The CPU sets the carry/borrow ﬂag when an addition operation produces a carry out of bit

7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and

branch, shift, and rotate — also clear or set the carry/borrow ﬂag.

0 No carry out of bit 7

1 Carry out of bit 7

CONDITION CODE REGISTER

CARRY

ZERO

NEGATIVE

INTERRUPT MASK

HALF-CARRY (FROM BIT 3)

TWO’S COMPLEMENT OVERFLOW

CCR

V1 1 H

N Z

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