MC9S08DZ96F2CLL datasheet(148/458 Pages) FREESCALE

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Chapter 7 Central Processor Unit (S08CPUV5)

MC9S08DZ128 Series Data Sheet, Rev. 1

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the high-order byte is located in the next memory location after the opcode, and the low-order byte is

located in the next memory location after that.

7.3.4

Direct Addressing Mode (DIR)

In direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page

(0x0000–0x00FF). During execution a 16-bit address is formed by concatenating an implied 0x00 for the

high-order half of the address and the direct address from the instruction to get the 16-bit address where

the desired operand is located. This is faster and more memory efﬁcient than specifying a complete 16-bit

address for the operand.

7.3.5

Extended Addressing Mode (EXT)

In extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of

program memory after the opcode (high byte ﬁrst).

7.3.6

Indexed Addressing Mode

Indexed addressing mode has seven variations including ﬁve that use the 16-bit H:X index register pair and

two that use the stack pointer as the base reference.

7.3.6.1

Indexed, No Offset (IX)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of

the operand needed to complete the instruction.

7.3.6.2

Indexed, No Offset with Post Increment (IX+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair as the address of

the operand needed to complete the instruction. The index register pair is then incremented

(H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is only used for MOV

and CBEQ instructions.

7.3.6.3

Indexed, 8-Bit Offset (IX1)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned

8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

7.3.6.4

Indexed, 8-Bit Offset with Post Increment (IX1+)

This variation of indexed addressing uses the 16-bit value in the H:X index register pair plus an unsigned

8-bit offset included in the instruction as the address of the operand needed to complete the instruction.

The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This

addressing mode is used only for the CBEQ instruction.

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