MC9S08DZ96F2CLL datasheet(136/458 Pages) FREESCALE

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Chapter 6 Parallel Input/Output Control

MC9S08DZ128 Series Data Sheet, Rev. 1

136

Freescale Semiconductor

6.5.10

Port K Registers

Port K is controlled by the registers listed below.

6.5.10.1

Port K Data Register (PTKD)

6.5.10.2

Port K Data Direction Register (PTKDD)

76543210

PTKD7

PTKD6

PTKD5

PTKD4

PTKD3

PTKD2

PTKD1

PTKD0

Reset:

00000000

Figure 6-60. Port K Data Register (PTKD)

Table 6-58. PTKD Register Field Descriptions

Field

Description

7:0

PTKD[7:0]

Port K Data Register Bits — For port K pins that are inputs, reads return the logic level on the pin. For port K

pins that are conﬁgured as outputs, reads return the last value written to this register.

Writes are latched into all bits of this register. For port K pins that are conﬁgured as outputs, the logic level is

driven out the corresponding MCU pin.

Reset forces PTKD to all 0s, but these 0s are not driven out the corresponding pins because reset also conﬁgures

all port pins as high-impedance inputs with pull-ups disabled.

76543210

PTKDD7

PTKDD6

PTKDD5

PTKDD4

PTKDD3

PTKDD2

PTKDD1

PTKDD0

Reset:

00000000

Figure 6-61. Port K Data Direction Register (PTKDD)

Table 6-59. PTKDD Register Field Descriptions

Field

Description

7:0

PTKDD[7:0]

Data Direction for Port K Bits — These read/write bits control the direction of port K pins and what is read for

PTKD reads.

0 Input (output driver disabled) and reads return the pin value.

1 Output driver enabled for port K bit n and PTKD reads return the contents of PTKDn.

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