MC9S08DZ96F2CLL datasheet(259/458 Pages) FREESCALE

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

259

SLPRQ5

Sleep Mode Request — This bit requests the MSCAN to enter sleep mode, which is an internal power saving

mode (see Section 12.5.5.4, “MSCAN Sleep Mode”). The sleep mode request is serviced when the CAN bus is

idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry

to sleep mode by setting SLPAK = 1 (see Section 12.3.2, “MSCAN Control Register 1 (CANCTL1)”). SLPRQ

cannot be set while the WUPIF ﬂag is set (see Section 12.3.4.1, “MSCAN Receiver Flag Register (CANRFLG)”).

Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN

detects activity on the CAN bus and clears SLPRQ itself.

0 Running — The MSCAN functions normally

1 Sleep mode request — The MSCAN enters sleep mode when CAN bus idle

INITRQ6,7

Initialization Mode Request — When this bit is set by the CPU, the MSCAN skips to initialization mode (see

Section 12.5.5.5, “MSCAN Initialization Mode”). Any ongoing transmission or reception is aborted and

synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1

(Section 12.3.2, “MSCAN Control Register 1 (CANCTL1)”).

The following registers enter their hard reset state and restore their default values: CANCTL08, CANRFLG9,

CANRIER10, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.

The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be

written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the

error counters are not affected by initialization mode.

When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the

MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN

is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.

Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after

initialization mode is exited, which is INITRQ = 0 and INITAK = 0.

0 Normal operation

1 MSCAN in initialization mode

1 The MSCAN must be in normal mode for this bit to become set.

2 See the Bosch CAN 2.0A/B speciﬁcation for a detailed deﬁnition of transmitter and receiver states.

3 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when

the CPU enters wait (CSWAI = 1) or stop mode (see Section 12.5.5.2, “Operation in Wait Mode” and Section 12.5.5.3,

“Operation in Stop Mode”)

4 The CPU has to make sure that the WUPE bit and the WUPIE wake-up interrupt enable bit (see Section 12.3.5, “MSCAN

Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.

5 The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).

6 The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).

7 In order to protect from accidentally violating the CAN protocol, the TXCAN pin is immediately forced to a recessive state when

the initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode

(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.

8 Not including WUPE, INITRQ, and SLPRQ.

9 TSTAT1 and TSTAT0 are not affected by initialization mode.

10 RSTAT1 and RSTAT0 are not affected by initialization mode.

Table 12-1. CANCTL0 Register Field Descriptions (continued)

Field

Description

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