MC9S08DZ96F2CLL datasheet(258/458 Pages) FREESCALE

258 / 458 page

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

258

Freescale Semiconductor

Table 12-1. CANCTL0 Register Field Descriptions

Field

Description

RXFRM1

Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message

correctly, independently of the ﬁlter conﬁguration. After it is set, it remains set until cleared by software or reset.

Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.

0 No valid message was received since last clearing this ﬂag

1 A valid message was received since last clearing of this ﬂag

RXACT

Receiver Active Status — This read-only ﬂag indicates the MSCAN is receiving a message. The ﬂag is

controlled by the receiver front end. This bit is not valid in loopback mode.

0 MSCAN is transmitting or idle2

1 MSCAN is receiving a message (including when arbitration is lost)2

CSWAI3

CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all

the clocks at the CPU bus interface to the MSCAN module.

0 The module is not affected during wait mode

1 The module ceases to be clocked during wait mode

SYNCH

Synchronized Status — This read-only ﬂag indicates whether the MSCAN is synchronized to the CAN bus and

able to participate in the communication process. It is set and cleared by the MSCAN.

0 MSCAN is not synchronized to the CAN bus

1 MSCAN is synchronized to the CAN bus

TIME

Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate.

If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the

active TX/RX buffer. As soon as a message is acknowledged on the CAN bus, the time stamp will be written to

the highest bytes (0x000E, 0x000F) in the appropriate buffer (see Section 12.4, “Programmer’s Model of

Message Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization

mode.

0 Disable internal MSCAN timer

1 Enable internal MSCAN timer

WUPE4

Wake-Up Enable — This conﬁguration bit allows the MSCAN to restart from sleep mode when trafﬁc on CAN is

detected (see Section 12.5.5.4, “MSCAN Sleep Mode”). This bit must be conﬁgured before sleep mode entry for

the selected function to take effect.

0 Wake-up disabled — The MSCAN ignores trafﬁc on CAN

1 Wake-up enabled — The MSCAN is able to restart

MC9S08DZ96F2CLL bảng dữ liệu(PDF) 258 Page - Freescale Semiconductor, Inc

MC9S08DZ96F2CLL bảng dữ liệu(HTML) 258 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL