MC9S08DZ96F2CLL datasheet(257/458 Pages) FREESCALE

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Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)

MC9S08DZ128 Series Data Sheet, Rev. 1

Freescale Semiconductor

257

Figure 12-3. CAN System

12.3

This section describes in detail all the registers and register bits in the MSCAN module. Each description

includes a standard register diagram with an associated ﬁgure number. Details of register bit and ﬁeld

function follow the register diagrams, in bit order. All bits of all registers in this module are completely

synchronous to internal clocks during a register read.

12.3.1

MSCAN Control Register 0 (CANCTL0)

The CANCTL0 register provides various control bits of the MSCAN module as described below.

NOTE

The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the

reset state when the initialization mode is active (INITRQ = 1 and

INITAK = 1). This register is writable again as soon as the initialization

mode is exited (INITRQ = 0 and INITAK = 0).

Read: Anytime

Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM

(which is set by the module only), and INITRQ (which is also writable in initialization mode).

76543210

RXFRM

RXACT

CSWAI

SYNCH

TIME

WUPE

SLPRQ

INITRQ

Reset:

00000001

= Unimplemented

Figure 12-4. MSCAN Control Register 0 (CANCTL0)

CAN Bus

CAN Controller

(MSCAN)

Transceiver

CAN node 1

CAN node 2

CAN node n

CAN_L

CAN_H

MCU

TXCAN

RXCAN

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