TBD datasheet(68/80 Pages) FREESCALE

68 / 80 page

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Hardware Design Considerations

Freescale Semiconductor

3.4.1.3

ECC Unused Pin Connections

When the error code corrected mechanism is not used in any 32- or 16-bit DDR configuration, refer to Table 58 to determine

the correct pin connections.

3.4.2

Serial RapidIO Interface Related Pins

3.4.2.1

Serial RapidIO interface Is Not Used

3.4.2.2

Serial RapidIO Specific Lane Is Not Used

Table 58. Connectivity of Unused ECC Mechanism Pins

Signal Name

Pin connection

MECC[0–7]

pull-up to VDDDDR

ECC_MDM

ECC_MDQS

pull-down to GND

ECC_MDQS

pull-up to VDDDDR

Table 59. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used

Signal Name

Pin Connection

SRIO_IMP_CAL_RX

GND

SRIO_IMP_CAL_TX

GND

SRIO_REF_CLK

GND

SRIO_REF_CLK

GND

SRIO_RXD[0–3]

GND

SRIO_RXD[0–3]

GND

SRIO_TXD[0–3]

VDDRIOPLL

GND

GNDRIOPLL

GND

GNDSXP

GND

GNDSXC

GND

VDDSXP

GND

VDDSXC

GND

Table 60. Connectivity of Serial RapidIO Related Pins When Specific Lane Is Not Used

Signal Name

Pin Connection

SRIO_IMP_CAL_RX

in use

SRIO_IMP_CAL_TX

in use

SRIO_REF_CLK

in use

SRIO_REF_CLK

in use

SRIO_RXDx

GNDSXC

SRIO_RXDx

GNDSXC

TBD bảng dữ liệu(PDF) 68 Page - Freescale Semiconductor, Inc

TBD bảng dữ liệu(HTML) 68 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

bảng dữ liệu tải về

Link URL