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TBD bảng dữ liệu(PDF) 37 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  Quad Core Digital Signal Processor
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Electrical Characteristics
MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
37
Table 23 summarizes the reset actions that occur as a result of the different reset sources.
2.7.3.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 32 CLKIN cycles after
VDD and VDDIO are both at their nominal levels.
2.7.3.2
Reset Configuration
The MSC8144E has two mechanisms for writing the reset configuration:
•
Through the I2C port
•
Through external pins
•
Through internal hard coded
Twenty-three signals (see Section 1 for signal description details) are sampled during the power-on reset sequence to define the
Reset Word Configuration Source and operating conditions:
•
RCW_SRC[2–0]
•
RC[16–0]
The RCFG_CLKIN_RNG pin must be valid during power-on or hard reset sequence. The STOP_BS pin must be always valid
and is also sampled during power-on reset sequence for RCW loading from an I
2C EEPROM.
Table 23. Reset Actions for Each Reset Source
Reset Action/Reset Source
Power-On Reset
(PORESET)
Hard Reset (HRESET)
Soft Reset (SRESET)
External only
External or Internal
(Software Watchdog,
Software or RapidIO)
External or
internal
Software
JTAG Command:
EXTEST, CLAMP, or
HIGHZ
Configuration pins sampled (Refer to
Section 2.7.3.2 for details).
Yes
NoNoNo
PLL state reset
Yes
No
No
No
Select reset configuration source
Yes
No
No
No
System reset configuration write
Yes
No
No
No
HRESET driven
Yes
Yes
No
No
IPBus modules reset (TDM, UART, SWT,
DDRC, IPBus master, GIC, HS, and GPIO)
Yes
Yes
Yes
Yes
SRESET driven
Yes
Yes
Yes
Depends on command
Extended cores reset
Yes
Yes
Yes
Yes
CLASS registers reset
Yes
Yes
Some
registers
Some registers
Timers, Performance Monitor
Yes
Yes
No
No
Packet Processor, PCI, DMA
Yes
Yes
Most
registers
Most registers



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