TBD datasheet(35/80 Pages) FREESCALE

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Electrical Characteristics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

2.7.1

Start-Up Timing

Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.7.2

describes the clocking characteristics. Section 2.7.3 describes the reset and power-up characteristics. You must use the

following guidelines when starting up an MSC8144E device:

•

PORESET and TRST must be asserted externally for the duration of the power-up sequence using the VDDIO (3.3 V)

supply. See Table 24 for timing. TRST deassertion does not have to be synchronized with PORESET deassertion.

During functional operation when JTAG is not used, TRST can be asserted and remain asserted after the power ramp.

Note:

For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the

VDDM3IO (2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information.

•

CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee correct device operation

(see Figure 7). 32 cycles should be accounted only after VDDIO reaches its nominal value.

•

CLKIN and PCI_CLK_IN should either be stable low during the power-up of VDDIO supply and start their swings after

power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows

during power-up.

Figure 7 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to toggle with the raise of VDDIO supply.

2.7.2

Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 20 shows the maximum frequency values for

internal (Core, Reference, Bus and DSI) and external (CLKIN, PCI_CLK_IN and CLKOUT. The user must ensure that

maximum frequency values are not exceeded.

Figure 7. Start-Up Sequence with VDD Raised Before VDDIO with CLKIN Started with VDDIO

Table 20. Clock Frequencies

Characteristic

Symbol

MIN

Max

Unit

CLKIN frequency

FCLKIN

150

MHz

PCI_CLK_IN frequency

FPCI_CLK_IN

150

MHz

CLKIN duty cycle

DCLKIN

PCI_CLK_IN duty cycle

DPCI_CLK_IN

Time

3.3 V

VDDIO Nominal

PORESET/TRST asserted

VDD Nominal

CLKIN starts toggling

VDD applied

PORESET

VDDIO applied

1.0 V

VDDIO = Nominal

VDD = Nominal

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