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TBD bảng dữ liệu(PDF) 52 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  Quad Core Digital Signal Processor
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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6
Freescale Semiconductor
52
Note: For some TDM modes transmit data is being output on other pins. This timing is valid for it as well. See the MSC8144E
Reference Manual
2.7.8
UART Timing
Figure 22 shows the UART input AC timing
Figure 23 shows the UART output AC timing
Figure 21. TDM Output Signals
Table 43. UART Timing
Characteristics
Symbol
Expression
Min
Max
Unit
URXD and UTXD inputs high/low duration
TUREFCLK
16
× TREFCLK
160
—
ns
URXD and UTXD inputs rise/fall time
TUAVKH
6ns
UTXD output rise/fall time
TUAVXH
5.5
ns
Note:
TUREFCLK = TREFCLK is guaranteed by design.
Figure 22. UART Input Timing
Figure 23. UART Output Timing
TDMxTCLK
TDMxTDAT
TDMxTSYN
tTDMDHOX
tTDMDHOV
tTDMDHOZ
tTDMHOX
tTDMC
tTDMCH
tTDMCL
tTDMSHOX
tTDMSHOV
UTXD, URXD
TUREFCLK
inputs
TUAVKH
TUAVKH
TUREFCLK
UTXD output
TUAVXH
TUAVXH



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