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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

2.7.11

ATM/UTOPIA/POS Timing

Table 52 provides the ATM/UTOPIA/POS input and output AC timing specifications.

Figure 33 provides the AC test load for the ATM/UTOPIA/POS.

Figure 34 shows the ATM/UTOPIA/UTOPIA timing with external clock.

Table 52. ATM/UTOPIA/POS AC Timing (External Clock) Specifications

Characteristic

Symbol

Min

Max

Unit

Outputs—External clock delay

tUEKHOV

Outputs—External clock High Impedance

tUEKHOX

Inputs—External clock input setup time

tUEIVKH

4ns

Inputs—External clock input hold time

tUEIXKH

1ns

Note:

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin. Although the specifications generally reference the rising edge of the clock, these AC timing diagrams also

apply when the falling edge is the active edge.

Figure 33. ATM/UTOPIA/POS AC Test Load

Figure 34. ATM/UTOPIAPOS AC Timing (External Clock)

Output

Z0 = 50 Ω

VDD/2

RL = 50 Ω

CLK (input)

tUEIXKH

tUEIVKH

tUEKHOV

Input Signals:

Output Signals:

tUEKHOX

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