TBD datasheet(53/80 Pages) FREESCALE

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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

2.7.9

Timer Timing

Figure 24 shows the timer input AC timing

2.7.10

Ethernet Timing

This section describes the AC electrical characteristics for the Ethernet interface.

There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is

a general configuration register 4 (GCR4) used to configure the timing. For additional information, see the MSC8144E

Reference Manual.

2.7.10.1

Management Interface Timing

Table 44. Timer Timing

Characteristics

Symbol

Min

Unit

TIMERx frequency

TTMREFCLK

10.0

TIMERx Input high phase

TTMCH

4.0

TIMERx Output low phase

TTMCL

4.0

Figure 24. Timer Timing

Table 45. Ethernet Controller Management Interface Timing

Characteristics

Symbol

Min

Max

Unit

ETHMDC clock pulse width high

tMDCH

—

ETHMDC to ETHMDIO delay2

tMDKHDX

ETHMDIO to ETHMDC rising edge set-up time

tMDDVKH

7—

ETHMDC rising edge to ETHMDIO hold time

tMDDXKH

0—

ETHMDC rise time.

tMDCR

—10

ETHMDC fall time.

tMDHF

—10

Notes:

Program the ETHMDC frequency (fMDC) to a maximum value of 2.5 MHz (400 ns period for tMDC). The value depends on the

source clock and configuration of MIIMCFG[MCS] and UPSMR[MDCP]. For example, for a source clock of 400 MHz, to

achieve fMDC = 2.5 MHz, program MIIMCFG[MCS] = 0x4 and UPSMR[MDCP] = 0. See the MSC8144E Reference Manual for

configuration details.

The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of

333 MHz, the delay is 58 ns.

TTMREFCLK

TTMCL

TTMCH

TIMERx (Input)

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