TBD datasheet(65/80 Pages) FREESCALE

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Hardware Design Considerations

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

3.1.2

Start-Up Timing

Section 2.7.1 describes the start-up timing.

3.2

Power Supply Design Considerations

3.2.1

PLL Supplies

Each PLL supply must have an external RC filter for the VDDPLL input. The filter is a 10 Ω resistor in series with two 2.2 μF,

low ESL (<0.5 nH) and low ESR capacitors. All three PLLs can connect to a single supply voltage source (such as a voltage

regulator) as long as the external RC filter is applied to each PLL separately (see Figure 44). For optimal noise filtering, place

the circuit as close as possible to its VDDPLL inputs. These traces should be short and direct.

Figure 44. PLL Supplies

3.2.2

Other Supplies (TBD)

3.3

Clock and Timing Signal Board Layout Considerations

When laying out the system board, use the following guidelines:

•

Keep clock and timing signal paths as short as possible and route with 50

Ω impedance.

•

Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following

equation to compute the resistor value:

Rterm = Rim – Rbuf

where Rim = trace characteristic impedance

Rbuf = clock buffer internal impedance.

Note:

See MSC8144 CLKIN and PCI_CLK_IN Board Layout (AN3440) for an example layout.

MSC8144

VDDPLL0

2.2

μF

2.2

μF

VDDPLL0

2.2

μF

2.2

μF

VDDPLL0

2.2

μF

2.2

μF

Voltage Regulator

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