TBD datasheet(62/80 Pages) FREESCALE

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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

2.7.14

JTAG Signals

Figure 39 Shows the Test Clock Input Timing Diagram

Figure 40 Shows the boundary scan (JTAG) timing diagram.

Table 55. JTAG Timing

Characteristics

Symbol

All frequencies

Unit

Min

Max

TCK cycle time

tTCKX

36.0

—

TCK clock high phase measured at VM = 1.6 V

tTCKH

15.0

—

TCK rise and fall times

tTCKR

—3.0

Boundary scan input data set-up time

tBSVKH

0.0

—

Boundary scan input data hold time

tBSXKH

15.0

—

TCK fall to output data valid

tTCKHOV

—

20.0

TCK fall to output high impedance

tTCKHOZ

—

24.0

TMS, TDI data set-up time

tTDIVKH

0.0

—

TMS, TDI data hold time

tTDIXKH

5.0

—

TCK fall to TDO data valid

tTDOHOV

—

10.0

TCK fall to TDO high impedance

tTDOHOZ

—

12.0

TRST assert time

tTRST

100.0

—

Note:

All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.

Figure 39. Test Clock Input Timing

Figure 40. Boundary Scan (JTAG) Timing

TCK

(Input)

tTCKX

tTCKH

tTCKR

TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

Input Data Valid

Output Data Valid

tBSXKH

tBSVKH

tTCKHOV

tTCKHOZ

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