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Electrical Characteristics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

all four cores. It was created using CodeWarrior® 3.0. These values are provided as examples only. Power consumption is

application dependent and varies widely. To assure proper board design with regard to thermal dissipation and maintaining

proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Section 3 of

this document.

At allowable voltage levels, Table 7 lists the estimated power dissipation on the 1.0-V AVDD supplies for the MSC8144E PLLs.

2.6

DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8144E.

2.6.1

DDR SDRAM DC Electrical Characteristics

This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144E.

Note:

DDR SDRAM uses VDDDDR(typ) = 2.5 V and DDR2 SDRAM uses VDDDDR(typ) = 1.8 V.

2.6.1.1

DDR2 (1.8 V) SDRAM DC Electrical Characteristics

Table 8 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144E when

VDDDDR(typ) = 1.8 V.

Table 7. MSC8144E PLLs Power Dissipation

PLL supply

Typical

Maximum

Unit

VDDPLL0

TBD

VDDPLL1

TBD

VDDPLL2

TBD

Note:

Typical value is based on VDDPLLX = 1.0 V, TA = 70°C, TJ = 105°C.

Table 8. DDR2 SDRAM DC Electrical Characteristics for VDDDDR (typ) = 1.8 V

Parameter/Condition

Symbol

Min

Max

Unit

I/O supply voltage1

VDDDDR

1.7

1.9

I/O reference voltage2

MVREF

0.49

× VDDDDR

0.51

× VDDDDR

I/O termination voltage3

VTT

MVREF –0.04

MVREF + 0.04

Input high voltage

VIH

MVREF + 0.125

VDDDDR +0.3

Input low voltage

VIL

–0.3

MVREF – 0.125

Output leakage current4

IOZ

–50

μA

Output high current (VOUT = 1.420 V)

IOH

–13.4

—

Output low current (VOUT = 0.280 V)

IOL

13.4

—

Notes:

VDDDDR is expected to be within 50 mV of the DRAM VDD at all times.

MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of VDDDDR.

Output leakage is measured with all outputs are disabled, 0 V

≤ V

OUT

≤ V

DDDDR.

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