TBD datasheet(61/80 Pages) FREESCALE

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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

Figure 37. SPI AC Timing in Master Mode (Internal Clock)

2.7.13

Asynchronous Signal Timing

The following interfaces use the specified asynchronous signals:

•

GPIO. Signals GPIO[31–0], when used as GPIO signals, that is, when the alternate multiplexed special functions are

not selected.

Note:

When used as a GPI, the input should be driven until it is acknowledged by the device; the GPIO input status is read

from a register.

•

EE port. Signals EE0, EE1, EE2_0, EE2_1, EE2_2, and EE2_3.

•

Boot function. Signal STOP_BS.

•

I2C interface. Signals I2C_SCL and I2C_SDA.

•

Interrupt inputs. Signals IRQ[15–0] and NMI.

•

Interrupt outputs. Signals INT_OUT and NMI_OUT (pulse width is 10 ns).

Figure 38 shows the behavior of the asynchronous signals.

Table 54. Signal Timing

Characteristics

Symbol

Type

Min

Input

tIN

Asynchronous

One CLKIN cycle1

Output

tOUT

Asynchronous

Application dependent

Note:

1. Relevant for EE0, IRQ[15–0], and NMI only.

Figure 38. Asynchronous Signal Timing

SPICLK (Output)

tNIIXKH

tNIKHOX

Input Signals:

SPIMISO

(See Note)

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

tNIIVKH

Output

tIN

Input

tOUT

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