TBD datasheet(57/80 Pages) FREESCALE

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MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

Figure 31. SMII Mode Signal Timing

2.7.10.6

RGMII AC Timing Specifications

Table 50 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.

Table 51 presents the RGMII AC timing specification for applications required non-delayed clock on board.

Table 50. RGMII with On-Board Delay AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

tSKEWT

-0.5

—

0.5

Data to clock input skew (at receiver) 2

tSKEWR

0.9

—

2.6

Clock cycle duration 3

tRGT

7.2

8.0

8.8

Duty cycle for 1000Base-T 4, 5

tRGTH/tRGT

Duty cycle for 10BASE-T and 100BASE-TX 3, 5

tRGTH/tRGT

Rise time (20%–80%)

tRGTR

—

0.75

Fall time (20%–80%)

tRGTF

—

0.75

GTX_CLK125 reference clock period

tG12

—8.0

—

GTX_CLK125 reference clock duty cycle

tG125H/tG125

—

Notes:

At recommended operating conditions with LVDD of 2.5 V +/- 5%.

This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will

be added to the associated clock signal.

For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.

Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

Duty cycle reference is LVdd/2.

This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.

GCR4 should be programmed as 0x00001004.

Table 51. RGMII with No On-Board Delay AC Timing Specifications

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Data to clock output skew (at transmitter)

tSKEWT

–2.6

—

–0.9

Data to clock input skew (at receiver) 2

tSKEWR

–0.5

—

0.5

Clock cycle duration 3

tRGT

7.2

8.0

8.8

Duty cycle for 1000Base-T 4, 5

tRGTH/tRGT

Duty cycle for 10BASE-T and 100BASE-TX 3, 5

tRGTH/tRGT

Rise time (20%–80%)

tRGTR

—

0.75

Fall time (20%–80%)

tRGTF

—

0.75

GTX_CLK125 reference clock period

tG12

—8.0

—

Valid

ETHCLOCK

ETHSYNC_IN

ETHRXD

ETHSYNC

ETHTXD

Valid

tSMXR

tSMDXKH

tSMDVKH

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