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Electrical Characteristics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 6

Freescale Semiconductor

2.7.7

TDM Timing

Figure 19 shows the TDM input AC timing.

Note: For some TDM modes receive data and receive sync are being input on other pins. This timing is valid for them as well.

See the MSC8144E Reference Manual.

Figure 20 shows TDMxTSYN AC timing in TSO=0 mode.

Figure 21 shows the TDM Output AC timing

Table 42. TDM Timing

Characteristic

Symbol

Expression

Min

Max

Units

TDMxRCLK/TDMxTCLK

tTDMC

TC1

—

TDMxRCLK/TDMxTCLK high pulse width

tTDMCH

(0.5

± 0.1) × TC4

7—

TDMxRCLK/TDMxTCLK low pulse width

tTDMCL

(0.5

± 0.1) × TC4

7—

TDM receive all input set-up time related to TDMxRCLK

TDMxTSYN input set-up time related to TDMxTCLK in TSO=0 mode

tTDMVKH

3.6

—

TDM receive all input hold time related to TDMxRCLK

TDMxTSYN input hold time related to TDMxTCLK in TSO=0 mode

tTDMXKH

1.9

—

TDMxTCLK high to TDMxTDAT output active2

tTDMDHOX

2.5

—

TDMxTCLK high to TDMxTDAT output valid2

tTDMDHOV

—9.8

All output hold time (except TDMxTSYN) 3

tTDMHOX

2.5

—

TDMxTCLK high to TDMxTDAT output high impedance2

tTDMDHOZ

—9.8

TDMxTCLK high to TDMxTSYN output valid2

tTDMSHOV

—9.25

TDMxTSYN output hold time3

tTDMSHOX

2.0

—

Notes:

Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.

Values are based on 20 pF capacitive load.

Values are based on 10 pF capacitive load.

The expression is for common calculations only.

Figure 19. TDM Inputs Signals

Figure 20. TDMxTSYN in TSO=0 mode

TDMxRCLK

TDMxRDAT

TDMxRSYN

tTDMC

tTDMCH

tTDMCL

tTDMVKH

tTDMXKH

TDMxTCLK

TDMxTSYN

tTDMVKH

tTDMXKH

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