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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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EB632 bảng dữ liệu(PDF) 17 Page - Freescale Semiconductor, Inc |
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EB632 bảng dữ liệu(HTML) 17 Page - Freescale Semiconductor, Inc |
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17 / 112 page  Clock System Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2 Freescale Semiconductor 17 6.2.2 2K87M Mask Set SCMR Field Definitions SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. — 26–31 —— Reserved Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 COREPDF COREMF BUSDF CPMDF Type R Reset — Bit 1617 18 192021 22 232425 26 272829 30 31 SPLLPDF SPLLMF — DLLDIS — COREDF Type R Reset — Figure 7. 2K87M Mask Set System Clock Mode Register (SCMR)—0x10C88 Table 11. 2K87M Mask Set SCMR Field Descriptions Name Bit No. Defaults Description Settings PORESET Hard Reset COREPDF 0–3 Configuration Pins Unaffected Core PLL Pre-Division Factor 0000 CPLL PDF = 1 0001 CPLL PDF = 2 0010 CPLL PDF = 3 0011 CPLL PDF = 4 All other combinations not used. COREMF 4–7 Configuration Pins Unaffected Core Multiplication Factor 0101 CPLL MF = 10 0110 CPLL MF = 12 0111 CPLL MF = 14 All other combinations not used. BUSDF 8–11 Configuration Pins Unaffected 60x-compatible Bus Division Factor 0001 Bus DF = 2 0010 Bus DF = 3 0011 Bus DF = 4 0100 Bus DF = 5 0101 Bus DF = 6 All other combinations not used. CPMDF 12–15 Configuration Pins Unaffected CPM Division Factor 0000 CPM DF = 1 0001 CPM DF = 2 0010 CPM DF = 3 All other combinations not used. SPLLPDF 16–19 Configuration Pins Unaffected SPLL Pre-Division Factor 0000 SPLL PDF = 1 0001 SPLL PDF = 2 0010 SPLL PDF = 3 0011 SPLL PDF = 4 0100 SPLL PDF = 5 0101 SPLL PDF = 6 All other combinations not used Table 10. 2K42A Mask Set SCMR Bit Descriptions (Continued) Name Bit No. Defaults Description Settings PORESET Hard Reset |
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