EB632 datasheet(29/112 Pages) FREESCALE

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HDI16

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

TREQ/HDM0

HREQ/HTREQ Pin Control

Controls the HREQ/HTREQ pin for host transmit data transfers. In non-

DMA (interrupt) mode (DMA = 0 in the HPCR), TREQ enables host

requests via the host request (HREQ or HTRQ) pin when the Transmit

Data Register Empty (TXDE) status bit in the ISR is set. If TREQ is

cleared, TXDE interrupts are disabled. If TREQ and TXDE are set, the

host request pin is asserted. In DMA modes (HPCR[DMA] = 1 and

HCR[HICR] = 1), software must set or clear TREQ to select the direction

of DMA transfers. Setting TREQ sets the direction of the DMA transfers

as host-to-core and enables the HREQ pin to request data transfers.

When HCR[HICR] is cleared and HPCR[DMA] is set, a TREQ read

reflects the status of NOT HDM0 in HCR. When written, TREQ affects

the INIT mode. See Table 25.

RREQ/HDM0

HREQ and HRREQ Pin Control

Controls the HREQ and HRREQ pins for host receive data transfers. In

non-DMA (interrupt) mode (HPCR[DMA] = 0), RREQ enables host

requests via the host request (HREQ or HRRQ) pin when the Receive

Data Register Full (RXDF) status bit in the ISR is set. If RREQ is cleared,

ISR[RXDF] interrupts are disabled. If RREQ is set, the host request pin

(HREQ or HRRQ) is asserted if ISR[RXDF] is set.

In host DMA mode (DMA = 1 in the HPCR and HICR = 1 in the HCR),

RREQ must be set or cleared by software to select the direction of DMA

transfers. Setting RREQ sets the direction of the host DMA transfers to

core-to-host and enables the HREQ pin to request data transfers. When

HICR in HCR is cleared and DMA in HPCR is set, RREQ, when read,

reflects the status of HDM0 in HCR.

When HCR[HICR] is cleared and HPCR[DMA] is cleared, an RREQ read

reflects the status of HCR[HDM0]. When written, RREQ affects the INIT

mode. See Table 25.

Table 24. Host-Side Registers After Reset

Name

Data

Reset Type

Hardware (HW)

Reset

Individual (IR)

Reset

ICR

All Bits

—

CVR

NMI

HV[0–6]

—

ISR

TXDE32

TXDE16

RXDF32

RXDF16

HREQ

1 if TREQ is set;

0 otherwise

HF[4–7]

—

TRDY

TXDE

RXDF

RX[0–3]

empty

TX[0–3]

empty

Table 23.

2K87M Mask Set ICR Bit Descriptions (Continued)

Name

Description

Settings

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