EB632 datasheet(34/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

HDI16

9.3

HREQ Logic Differences

The following sections describe the implementation of HREQ logic for the 2K42A and 2K87M mask sets.

9.3.1 2K42A Mask Set HREQ Logic

When HREQ is connected to the host processor interrupt input, the HDI16 asserts HREQ to request service from

the host processor. HREQ is asserted when TXDE is set and/or ISR[RXDF] is set, and the corresponding enable bit

(TREQ or RREQ, respectively) is set, as Figure 9 shows.

The host processor acknowledges host interrupts by executing an interrupt service routine. The host processor tests

ISR[RXDF] and ISR[TXDE] to determine the interrupt source. The host processor interrupt service routine must

read or write the appropriate HDI16 data register to clear the interrupt. HREQ is deasserted under the following

conditions:

•

The enabled request is cleared or masked.

•

The SC140 core is reset.

9.3.2 2K87M Mask Set HREQ Logic

When HREQ is connected to the host processor interrupt input, the HDI16 asserts HREQ to request service from

the host processor. HREQ is asserted according to the programming of ICR[HTRA] and the status bits TXDE,

TXDE16, and TXDE2 when ICR[TREQ] is set, or according to the programming of ICR[HRRA] and the status

bits RXDF, RXDF16, and RXDF32 when ICR[RREQ] is set, as Figure 10 shows. The programming of HRRA or

HTRA chooses the status bit, and depending on its value, HREQ is asserted or deasserted.

Figure 9. HDI16 Host Request Structure

TREQ

RREQ

ICR

Enable

815

INIT

Status

TRDY

TXDE

RXDF

ISR

HREQ

Host Request

Asserted

HRRQ

HREQ

HTRQ

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