EB632 datasheet(14/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Clock System

6.1

Clock Scheme Modifications

The MSC8101 mask set 2K42A and the MSC8103 mask set 2K87M use different clock schemes. The following

paragraphs describe the clock schemes.

6.1.1 Mask Set 2K42A Clock Scheme

Six bit values map the MSC8101 clocks to one of the valid configuration mode options. Each option determines the

CLKIN

, SC140 core, system bus, SCC clock, CPM, and CLKOUT frequencies. The six bit values are derived from

three dedicated input pins (MODCK[1–3]) and three bits from the reset configuration word (MODCK_H). To

configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140 core, SCC

clocks, CPM parallel I/O ports, and system buses, the MODCK[1–3] pins are sampled and combined with the

MODCK_H values when the internal power-on reset (internal PORESET) is deasserted. Clock configuration

changes only when the internal PORESET signal is deasserted.

The following factors are configured:

•

SPLL pre-division factor (SPLL PDF)

•

SPLL multiplication factor (SPLL MF)

•

Bus post-division factor (Bus DF)

Figure 4 shows the functional block diagram for the 2K42A mask set. The 2K42A mask set contains an internal

system phase-lock loop (SPLL)

The SCC division factor (SCC DF) is fixed at 4 and the CPM division factor (CPM DF) is fixed at 2. The BRG

division factor (BRG DF) is configured through the System Clock Control Register (SCCR) and can be 4, 16

(default after reset), 64, or 256.

Figure 4. MSC8101 Clock Functional Block Diagram for 2K42A Mask Set

System Bus Clock

CPM Clock

CLKIN

× f

CPM

× f CPM

SCC Clock

BRG Clock

CLKOUT

SC140 Core Clock

Bus

SCC

SPLL

PDF

SPLL

BRG

CKO

CPM

DLL

Note:

SPLL PDF determined by the clock configuration mode; SPLL MF determined by the clock

configuration mode; Bus DF = CLKOUT DF and is 4 or 5, determined by the clock configuration

mode; SCC DF is always 4; CPM DF is always 2; BRG DF is set by the System Clock Control

Key:

SPLL PDF: System PLL Pre-Division Factor

SPLL MF: System PLL Multiplication Factor

DLL: Delay Lock Loop

Bus DF: Bus Division Factor

SCC DF: SCC Division Factor

CPM DF: CPM Division Factor

BRG DF: Baud Rate Generator Division Factor

CKO DF: CLKOUT Division Factor

DLLIN

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