EB632 datasheet(27/112 Pages) FREESCALE

27 / 112 page

HDI16

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

ICR is a read/write control register that allows the use of bit manipulation instructions on control register bits. The

host processor uses the ICR to control the HDI16 interrupts and flags. The SC140 core cannot access the ICR. The

HPCR[DMA] bit and the HCR[HICR] bit control the function of the ICR bits.

Table 23.

2K87M Mask Set ICR Bit Descriptions

Name

Description

Settings

HRRA

0–1

HDI Receive Request Assertion

The receive request is asserted a specified time based on the number of

data bytes to receive.

HRRQ asserted for 8 bytes (RX full)

HRRQ asserted for 16 bytes (RX full + 1

HOTX entry full)

HRRQ asserted for 32 bytes (RX full + 3

HOTX entries full)

Reserved

HTRA

2–3

HDI Transmit Request Assertion

The transmit request is asserted a specified time based on the number of

data bytes to transmit.

HTRQ/HREQ asserted for 8 bytes (TX

empty)

HTRQ/HREQ asserted for 16 bytes (TX

empty + 1 HOTX entry empty)

HTRQ/HREQ asserted for 32 bytes (TX

empty + 3 HOTX entries empty)

Reserved

—

Reserved. Write to zero for future compatibility.

HF0

Host Flag 0

A general-purpose flag for host-to-core communication. The host

processor can set or clear HF0. HF0 is reflected in the HSR on the core

side of the HDI16.

HF1

Host Flag 1

A general-purpose flag for host-to-core communication. The host

processor can set or clear HF1. HF1 is reflected in the HSR on the core

side of the HDI16.

—

Reserved. Write to zero for future compatibility.

INIT

Force Initialization

Used by the host processor to force initialization of the HDI16 hardware

(which may or may not be necessary, depending on the software design

of the interface). During initialization, the HDI16 transmit and receive

control bits are configured. The type of initialization performed when the

INIT bit is set depends on the state of TREQ and RREQ in the HDI16.

The INIT command, which is local to the HDI16, conveniently configures

the HDI16 into the desired data transfer mode. The effect of the INIT

command is described in Table 25 on page 30. When the host sets the

INIT bit, the HDI16 hardware executes the INIT command. The interface

hardware clears the INIT bit after the command executes.

EB632 bảng dữ liệu(PDF) 27 Page - Freescale Semiconductor, Inc

EB632 bảng dữ liệu(HTML) 27 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL