EB632 datasheet(66/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Errata

CPM40

Corruption in AAL0 IDLE Cell

Date Added: 5/30/2000

Description: There is a rare case when transmitting an ATM idle cell that the idle cell may be

corrupted. This can occur in certain internal sequences of events that cannot be controlled or de-

tected by the user.

Workaround: Place the Idle Base template at address 64 byte align minus 4. For example use

Idle_BASE = 0x2cfc not 0x2d00.

System Number: 4648b

0K40A

1K42A

2K42A

CPM41

Limitation in ATM Controller

Date Added: 5/30/2000

Description: There are some limitations in the ATM controller. The first limitation is that only

the first 8 PM tables can be used instead of 64. When using these 8 tables, the user must clear the

5 most significant bits of TBD_BASE (in case of Tx PM) or RBD_BASE (in case of Rx PM). The

second limitation is that only the first 2048 ATM channel numbers can be used.

Workaround: There is a microcode patch that can fix the PM limitation. The ATM channel

number limitation has no workaround.

System Number: 4744

0K40A

1K42A

2K42A

CPM42

Data Corruption in MCC

Date Added: 5/30/2000

Description: Data corruption may occur in the receive buffers of MCC channels when more then

one TDM slot uses 7 bits of contiguous data.

Workaround: It is possible to avoid this problem by splitting the 7 bits slots between two SI ram

entries such that one entry will represent 4 bits of the slot and the other SI entry will represent 3

bits of the slot. The errata occurs only when all the 7 bits are represented by one entry in the SI

ram.

System Number: 4743

0K40A

1K42A

2K42A

CPM43

TxCLAV Ignored By UTOPIA in Single PHY Mode

Date Added: 5/30/2000

Description: When the FCC transmitter is configured to work in UTOPIA single PHY master

mode, it ignores deassertion of the TxCLAV signal. Therefore, the UTOPIA slave cannot control

the flow of cells by deasserting TxCLAV. Note that this bug affects Rev A.1 chips only.

Workaround: Configure the FCC to work in multi-master mode but limit the number of PHYs

to 1 by programming: FPSMR[LAST PHY] = 5’b0

System Number: 4882

0K40A

1K42A

2K42A

CPM44

Zero Insertion Error on MCC

Date Added: 5/30/2000

Description: When the MCC transmitter is used in HDLC super channel mode, a zero insertion

at the last bit before the flag fails to occur.

Workaround: There is a microcode patch which fixes the problem.

System Number: 4941

0K40A

1K42A

2K42A

Table 48. Errata Resolved in Mask Set 2K87M (Continued)

Errata

Number

Errata Description

Applies

to Mask

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