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EB632 bảng dữ liệu(PDF) 26 Page - Freescale Semiconductor, Inc |
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EB632 bảng dữ liệu(HTML) 26 Page - Freescale Semiconductor, Inc |
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26 / 112 page ![]() Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2 26 Freescale Semiconductor HDI16 Table 22 shows the valid HM values and their meaning. 9.1.2 2K87M Mask Set ICR Definitions Table 22. HM Host DMA Mode Values (HICR=1) HM Mode 0 1 DMA Mode Non-DMA Mode 0 0 16-bit words 64-bit words. Last read/write (trigger) address: 0x4 0 1 32-bit words 48-bit words. Last read/write (trigger) address: 0x5 1 0 48-bit words 32-bit words. Last read/write (trigger) address: 0x6 1 1 64-bit words 16-bit words. Last read/write (trigger) address: 0x7 ICR 2K87M Mask Set Interface Control Register (DMA = 0, HICR = 1) 0x0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HRRA HTRA — HF0 HF1 — INIT HM HF2 HF3 HDRQ TREQ RREQ Type R/W Reset See Table 24 on page 29 ICR 2K87M Mask Set Interface Control Register (DMA = 1, HICR = 1) 0x0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HRRA HTRA — HF0 HF1 — INIT HM HF2 HF3 — TREQ RREQ Type R/W Reset See Table 24 on page 29 ICR 2K87M Mask Set Interface Control Register (DMA = 0, HICR = 0) 0x0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HRRA HTRA — HF0 HF1 — INIT HDM HF2 HF3 HDRQ TREQ RREQ Type R/W R R/W Reset See Table 24 on page 29 ICR 2K87M Mask Set Interface Control Register (DMA = 1, HICR = 0) 0x0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HRRA HTRA — HF0 HF1 — INIT HDM HF2 HF3 — Note 1 Note 2 Type R/W R R/W R/W Reset See Table 24 on page 29 Notes: 1. HDM0 when read, TREQ when written 2. HDM0 when read, RREQ when written |
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