EB632 datasheet(51/112 Pages) FREESCALE

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CPM

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Table 38 describes TCGSR fields.

14.4.19 TC Layer Cell Counters

Each TC block maintains six memory-mapped 16-bit performance cell counters listed in Table 39 that are updated

during operation and can be read by the host. If a counter overflows, it wraps back to zero and generates a maskable

interrupt. These counters are automatically cleared when read if TCMODE[CM] = 0; see Section 14.4.12.

14.4.20 Programming FCC2

FCC2 is designed to work with the TC blocks. The TC blocks are located on fixed addresses on the UTOPIA bus

internally. FCC2 should be programmed to work with the TC blocks as if the TC blocks are external PHYs located

on the lowest eight (or fewer) addresses.

Table 38. TCGSR Field Descriptions

Name

Description

Settings

CD1

Cell Delineation

The cell delineation state machine status of

TC1.

Cell delineation state machine is in Hunt or Pre-Synch mode.

Cell delineation machine is in Synch mode.

—

1–4

Reserved. Write to 0 for future compatibility.

CD6

Cell Delineation

The cell delineation state machine status of

TC6.

Cell delineation state machine is in Hunt or Pre-Synch mode.

Cell delineation machine is in Synch mode.

CD7

Cell Delineation

The cell delineation state machine status of

TC7.

Cell delineation state machine is in Hunt or Pre-Synch mode.

Cell delineation machine is in Synch mode.

CD8

Cell Delineation

The cell delineation state machine status of

TC8.

Cell delineation state machine is in Hunt or Pre-Synch mode.

Cell delineation machine is in Synch mode.

8–15

Reserved. Write to 0 for future compatibility.

Table 39. TC Performance Cell Counters

Counter Name

Description

Received Cell Counter (RCC)

This cell counter is updated whenever a received cell without HEC errors is passed to the Rx

UTOPIA FIFO.

Transmitted Cell Counter (TCC)

This cell counter is updated whenever the transmission of a cell is completed.

Errored Cell Counter (ECC)

This cell counter is updated whenever a received errored cell (cell with header error) is discarded.

Corrected Cell Counter (CCC)

This cell counter is updated whenever a received cell with a HEC single bit error is corrected. If

header single bit error correction is not enabled (TCMODE[SBC] is set), this counter is not updated.

(All errored cells are counted by the errored cell counter (ECC).)

Tx IDLE Cell Counter (ICC)

This cell counter is updated whenever an idle cell is transmitted.

Filtered Cell Counter (FCC)

This cell counter is updated whenever an idle/unassigned cell is filtered (discarded). If cell filters are

not enabled (TCMODE[CF] is cleared), this counter is not updated.

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