EB632 datasheet(60/112 Pages) FREESCALE

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Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

Errata

BOOT2

Boot Interference in Multi-Master System with Shared Memory

Date Added: 8/5/2001

Description: The DSPRAM address in the memory map as programmed by the boot loader code

in the ROM is the same for all processors. During simultaneous boot, this will cause interference

of one processor with another.

Workaround: For up to 4 MSC8101’s including the configuration master.

Boot the processors one after the other, and not at the same time. Reprogram unique DSPRAM

address for each processor. The configuration master is set also to be the arbitration master and

the memory controller for the system. The configuration word for the master should set the MMR

field of the reset word (bits [18:19]) to 2'b11. This will mask all the external bus requests of the

configuration slaves. After the master completes its boot, the user should:

Clear all external requestors from the Arbitration Level Register (ALR) of the arbi-

tration master.

Reprogram the UPM of the DSPRAM bank to unique address (see programming

example below)

Set priority for the next configuration slave in the Arbitration Level Register (ALR)

of the arbitration master.

Enable external bus requests by clearing SIUMCR MMR field (bits [16:17]).

Repeat stages 2,3 for consecutive slaves.

Configuration master programming code:

move.l PPC_ALRH,D7 ; Step #1

move.l PPC_ALRL,D8

bmclr.w #$f,D7.L

bmclr.w #$ff00,D8.H

move.l D7,PPC_ALRH

move.l D8,PPC_ALRL

upmc_init $04000000 ; Step #2 (DSPRAM base address

$0400_0000)

move.l PPC_ALRH,D7 ; Step #3

nop

bmset.w #$7,D7.L

nop

move.l D7,PPC_ALRH

move.l SIUMCR,D7; Step #4

nop

bmclr.w #$c000,D7.L

nop

move.l D7,SIUMCR

0K40A

1K42A

2K42A

GEN1

Device Withstands MM ESD of 75V Instead of 100V

Date Added: 5/21/2002

Description: Device meets the ESD specifications for Human Body Model (HBM) of 1000V and

Charged Device Model (CDM) of 500V but does not withstand the Machine Model (MM) re-

quirement of 100V. All pins guaranteed to withstand 75V MM.

Workaround: None.

0K40A

1K42A

2K42A

Table 48. Errata Resolved in Mask Set 2K87M (Continued)

Errata

Number

Errata Description

Applies

to Mask

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