EB632 datasheet(57/112 Pages) FREESCALE

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Errata

Functional Differences Between MSC8101 (Mask 2K42A) and MSC8103 (Mask 2K87M), Rev. 2

Freescale Semiconductor

SIU8

Parity Checking Error

Date Added: 6/13/2000:

Description: During a read from a device with port size less than 64 bits, from an address not

aligned to 64 bits, the parity bits for parity check are not taken from the correct locations. For ex-

ample, for a read of 4 bytes from a 32-bit port size from address 4, the parity is checked against

DP[4–7] while it should be checked against DP[0–3]. The bug exists for both normal and rmw

parity, and for both System and Local buses.

Workaround: None

System Number: 5839

0K40A

1K42A

2K42A

SIU9

Bus Monitor Asserts Spurious TEA After Address Retry.

Date Added: 1/28/2001

Description: The bus monitor will not recognize the competition of an Address Retry transaction

and will assert TEA if there is no bus activity for a time equal to the expiration time.

Workaround: Disable the bus monitor in systems where Address Retry cycles are used (e.g. sys-

tems which include PowerSpan).

0K40A

1K42A

2K42A

SIU10

Strict Enforcement of Requirement to Assert DBG and TS in Same Cycle When Core En-

abled

Date Added: 1/28/2001

Description: This is a compatibility note. An external arbiter must assert DBG in the same clock

in which TS is asserted (there may be a one clock delay if the PPC_ACR[DBGD] bit is set, how-

ever, after reset this bit is not set by default). Some external arbiters, including the one implement-

ed in PowerSpan, violate this requirement. As a result, the system hangs following the first bus

access after reset.

Workaround: Use only a compliant external arbiter or the internal MSC8101 arbiter.

0K40A

1K42A

2K42A

QSIU3

TEA May Hang 60x-Compatible Bus

Date Added: 5/30/2000

Description: TEA may hang the 60x-compatible bus if it is asserted between specific address and

data phases during a split transaction.

Workaround: Enable Bus Monitor.

Fix Plan: Rev. A

0K40A

1K42A

2K42A

QSIU5

Incorrect Data on 60x-Compatible Bus

Date Added: 6/13/2000

Description: The following sequence on the 60x-compatible bus can result in incorrect data:

Read transaction with DACK before AACK.

Failed atomic write transaction.

Write transaction.

Workaround: None.

System Number: 5823

0K40A

1K42A

2K42A

Table 48. Errata Resolved in Mask Set 2K87M (Continued)

Errata

Number

Errata Description

Applies

to Mask

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