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SH79F024XU bảng dữ liệu(PDF) 77 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU bảng dữ liệu(HTML) 77 Page - SINOWEALTH Electronic Ltd |
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77 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 77 8.8.4 8.8.4 8.8.4 8.8.4 Registers Registers Registers Registers Table Table Table Table 8 8 8 8....27 27 27 27 Power Control Register Table Table Table Table 8 8 8 8....28 28 28 28 Suspend Mode Control Register Example: Example: Example: Example: 87H 87H 87H 87H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 PCON PCON PCON PCON SMOD SSTAT - - GF1 GF0 PD IDL R/W R/W R/W R/W R/W R/W - - R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 - - 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7 7 7 7 SMOD SMOD SMOD SMOD Baud Baud Baud Baud rate rate rate rate double double double double bit bit bit bit 6 6 6 6 SSTAT SSTAT SSTAT SSTAT SCON SCON SCON SCON [7:5] [7:5] [7:5] [7:5] function function function function selection selection selection selection bit bit bit bit 3-2 3-2 3-2 3-2 GF[1:0] GF[1:0] GF[1:0] GF[1:0] General General General General purpose purpose purpose purpose flags flags flags flags for for for for software software software software use use use use 1 1 1 1 PD PD PD PD Power-Down Power-Down Power-Down Power-Down mode mode mode mode control control control control bit bit bit bit 0: Cleared by hardware when an interrupt or reset occurs 1: Set by software to activate the Power-Down mode 0 0 0 0 IDL IDL IDL IDL Idle Idle Idle Idle mode mode mode mode control control control control bit bit bit bit 0: Cleared by hardware when an interrupt or reset occurs 1: Set by software to activate the Idle mode 8EH 8EH 8EH 8EH Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 SUSLO SUSLO SUSLO SUSLO SUSLO.7 SUSLO.6 SUSLO.5 SUSLO.4 SUSLO.3 SUSLO.2 SUSLO.1 SUSLO.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 0 0 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7-0 7-0 7-0 7-0 SUSL SUSL SUSL SUSLO O O O[[[[7 7 7 7::::0 0 0 0]]]] This register is used to control the CPU enter suspend mode (Idle or Power- Down). Only consecutive instructions like below will make CPU enter suspend mode. Other wise the either SUSLO, IDL or PD bit will be cleared by hardware in the next machine cycle. IDLE_MODE: MOV SUSLO, #55H ORL PCON, #01H NOP NOP NOP POWERDOWN_MODE: MOV SUSLO, #55H ORL PCON, #02H NOP NOP NOP |
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