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SH79F024XU bảng dữ liệu(PDF) 63 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU bảng dữ liệu(HTML) 63 Page - SINOWEALTH Electronic Ltd |
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63 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 63 The Given address for slave 1 and 2 differ in the LSB. For slave 1, it is a don’t care, while for slave 2 it is 1. Thus to communicate only with slave 1, the master must send an address with LSB = 0 (10100000). Similarly the bit 1 is 0 for slave 1 and don’t care for slave 2. Hence to communicate only with slave 2 the master has to transmit an address with bit 1 = 1 (1010 0011). If the master wishes to communicate with both slaves simultaneously, then the address must have bit 0 = 1 and bit 1 = 0. The bit 2 position is don’t care for both the slaves. This allows two different addresses to select both slaves (1010 0001 and 1010 0101). The master can communicate with all the slaves simultaneously with the Broadcast Address. This address is formed from the logical OR of the SADDR and SADEN. The zeros in the result are defined as don’t cares. In most cases, the Broadcast Address is FFh, this address will be acknowledged by all slaves. On reset, the SADDR and SADEN are initialized to 00h. This results in Given Address and Broadcast Address being set as XXXXXXXX (all bits don’t care). This effectively removes the multiprocessor communications feature, since any selectivity is disabled. This ensures that the EUART 0 will reply to any address, which it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. So the user may implement multiprocessor by software address recognition mentioned above. 8.2.5 8.2.5 8.2.5 8.2.5 Error Error Error Error Detection Detection Detection Detection Error detection is available when the SSTAT bit in register PCON is set to logic 1.The SSTAT bit must be logic 1 to access any of the status bits (FE, RXOV, and TXCOL). The SSTAT bit must be logic 0 to access the Mode Select bits (SM0, SM1, and SM2).All the 3 bits should be cleared by software after they are set, even when the following frames received without any error will not be cleared automatically. Transmit Transmit Transmit Transmit Collision Collision Collision Collision The Transmit Collision bit (TXCOL bit in register SCON) reads ‘1’ if RI is set 0 and user software writes data to the SBUF register while a transmission is still in progress. If this occurs, the new data will be ignored and the transmit buffer will not be written. Receive Receive Receive Receive Overrun Overrun Overrun Overrun The Receive Overrun bit (RXOV in register SCON) reads ‘1’ if a new data byte is latched into the receive buffer before software has read the previous byte. The previous data is lost when this happen. Frame Frame Frame Frame Error Error Error Error The Frame Error bit (FE in register SCON) reads ‘1’ if an invalid (low) STOP bit is detected. Break Break Break Break Detection Detection Detection Detection A break is detected when any 11 consecutive bits are sensed low. Since a break condition also satisfies the requirements for a framing error, a break condition will also result in reporting a framing error. Once a break condition has been detected, the EUART will go into an idle state and remain in this idle state until a valid stop bit (rising edge on RxD line) has been received. 8.2.6 8.2.6 8.2.6 8.2.6 Register Register Register Register Table Table Table Table 8 8 8 8....16 16 16 16 Power Control Register 87 87 87 87H H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 P P P PCON CON CON CON SMOD SSTAT - - GF1 GF0 PD IDL R/W R/W R/W R/W R/W R/W - - R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 - - 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7 7 7 7 SMOD SMOD SMOD SMOD Baud Baud Baud Baud rate rate rate rate doubler doubler doubler doubler If set in mode 1 & 3, the baud-rate of EUART is doubled if using timer 1 as baud-rate generator If set in mode 2, the baud-rate of EUART is doubled 6 6 6 6 SSTAT SSTAT SSTAT SSTAT SCON SCON SCON SCON [7:5] [7:5] [7:5] [7:5] function function function function select select select select bit bit bit bit 0: SCON [7:5] operates as SM0, SM1, SM2 1: SCON [7:5] operates as FE, RXOV, TXCOL 3-2 3-2 3-2 3-2 GF[1:0] GF[1:0] GF[1:0] GF[1:0] General General General General purpose purpose purpose purpose flag flag flag flags s s s for for for for software software software software use use use use 1 1 1 1 PD PD PD PD Power-Down Power-Down Power-Down Power-Down m m m mode ode ode ode control control control control bit bit bit bit 0 0 0 0 IDL IDL IDL IDL Idle Idle Idle Idle m m m mode ode ode ode control control control control bit bit bit bit |
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