SH79F024XU datasheet(43/92 Pages) SINOWEALTH

43 / 92 page

SH79F

SH79F082

082

Table

Table 8

8....2

2 PWM Module Control Register

In edge-aligned mode, PWM waveform diagram with different PWMS is shown below.

PWMn output

(PWMnS = 0)

n = 1 or 2

PWMn1 output

(PWMn1S = 0)

Duty

Period

PWMn output

(PWMnS = 1)

PWMn1 output

(PWMn1S = 1)

D9H

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

PWMCON

PWMCLK1 PWMCLK0 PWM21S

PWM11S

PWM2S

PWM1S

R/W

Reset

Reset Value

Value

((((POR/WDT/LVR

POR/WDT/LVR

POR/WDT/LVR/PIN

/PIN

/PIN))))

Bit

Bit Number

Number

Bit

Bit Mnemonic

Mnemonic

Description

7----6

PWMCLK

PWMCLK[[[[1

1:0]

:0]

PWM

PWM Module

Module

Module clock

clock

clock select

select

select bit

bit

00: PWM clock = System clock/1

01: PWM clock = System clock/2

10: PWM clock = System clock/4

11: PWM clock = System clock/8

PWM21S

PWM

PWM2

1 output

output

output mode

mode

mode select

select

select bit

bit

0: Driver circuit High Active, PWM21 output low during duty time, output high

during remain period time

1: Driver circuit Low Active, PWM21 output high during duty time, output low

during remain period time

PWM11S

PWM

PWM1

1 output

output

output mode

mode

mode select

select

select bit

bit

0: Driver circuit High Active, PWM11 output low during duty time, output high

during remain period time

1: Driver circuit Low Active, PWM11 output high during duty time, output low

during remain period time

PWM2S

PWM

PWM2

2 output

output

output mode

mode

mode select

select

select bit

bit

0: Driver circuit High Active, PWM2 output high during duty time, output low

during remain period time

1: Driver circuit Low Active, PWM2 output low during duty time, output high

during remain period time

PWM1S

PWM

PWM1

1 output

output

output mode

mode

mode select

select

select bit

bit

0: Driver circuit High Active, PWM1 output high during duty time, output low

during remain period time

1: Driver circuit Low Active, PWM1 output low during duty time, output high

during remain period time

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