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SH79F024XU bảng dữ liệu(PDF) 68 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU bảng dữ liệu(HTML) 68 Page - SINOWEALTH Electronic Ltd |
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68 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 68 Table Table Table Table 8 8 8 8....22 22 22 22 ADC Time Control Register Note: Note: Note: Note: (1) Make sure that tAD ≧1µs; (2) The minimum sample time is 2 tAD, even TS[3:0] = 0000; The maximum sample time is 15 tAD, even TS[3:0] = 1111; (3) Evaluate the series resistance connected with ADC input pin before set TS[3:0]; (4) Be sure that the series resistance connected with ADC input pin is no more than 10kΩ when 2 tAD sample time is selected; (5) Total conversion time is: 12 tAD + sample time. For For For For Example: Example: Example: Example: 94H 94H 94H 94H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 ADT ADT ADT ADT TADC2 TADC1 TADC0 - TS3 TS2 TS1 TS0 R/W R/W R/W R/W R/W R/W R/W - R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 0 - 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7-5 7-5 7-5 7-5 TADC[2:0] TADC[2:0] TADC[2:0] TADC[2:0] ADC ADC ADC ADC Clock Clock Clock Clock Period Period Period Period Select Select Select Select bits bits bits bits 000: ADC Clock Period tAD = 2 tSYS 001: ADC Clock Period tAD = 4 tSYS 010: ADC Clock Period tAD = 6 tSYS 011: ADC Clock Period tAD = 8 tSYS 100: ADC Clock Period tAD = 12 tSYS 101: ADC Clock Period tAD = 16 tSYS 110: ADC Clock Period tAD = 24 tSYS 111: ADC Clock Period tAD = 32 tSYS 3-0 3-0 3-0 3-0 TS[3:0] TS[3:0] TS[3:0] TS[3:0] Sample Sample Sample Sample time time time time select select select select bits bits bits bits 2 tAD ≤ Sample time = (TS[3:0]+1) * tAD ≤ 15 tAD System System System System Clock Clock Clock Clock (SYSCLK) (SYSCLK) (SYSCLK) (SYSCLK) TADC[2:0] TADC[2:0] TADC[2:0] TADC[2:0] ttttAD AD AD AD TS[3:0] TS[3:0] TS[3:0] TS[3:0] Sample Sample Sample Sample Time Time Time Time Conversion Conversion Conversion Conversion Time Time Time Time 4MHz 000 0.25*2=0.5µs - - ( tAD<1µs, not recommended) 001 0.25*4=1µs 0000 2*1=2µs 12*1+2=14µs 001 0.25*4=1µs 0111 8*1=8µs 12*1+8=20µs 001 0.25*4=1µs 1111 15*1=15µs 12*1+15=27µs 111 0.25*32=8µs 0000 2*8=16µs 12*8+16=112µs 111 0.25*32=8µs 0111 8*8=64µs 12*8+64=160µs 111 0.25*32=8µs 1111 15*8=120µs 12*8+120=216µs 8MHz 000 0.125*2=0.25µs - - ( tAD<1µs, not recommended) 011 0.125*8=1µs 0000 2*1=2µs 12*1+2=14µs 011 0.125*8=1µs 0111 8*1=8µs 12*1+8=20µs 011 0.125*8=1µs 1111 15*1=15µs 12*1+15=27µs 111 0.125*32=4µs 0000 2*4=8µs 12*4+8=56µs 111 0.125*32=4µs 0111 8*4=32µs 12*4+32=80µs 111 0.125*32=4µs 1111 15*4=60µs 12*4+60=108µs 12MHz 000 0.083*2=0.166µs - - ( tAD<1µs, not recommended) 100 0.083*12=1µs 0000 2*1=2µs 12*1+2=14µs 100 0.083*12=1µs 0111 8*1=8µs 12*1+8=20µs 100 0.083*12=1µs 1111 15*1=15µs 12*1+15=27µs 111 0.083*32=2.7µs 0000 2*2.7=5.4µs 12*2.7+5.4=37.8µs 111 0.083*32=2.7µs 0111 8*2.7=21.6µs 12*2.7+21.6=54µs 111 0.083*32=2.7µs 1111 15*2.7=40.5µs 12*2.7+40.5=72.9µs |
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