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SH79F024XU bảng dữ liệu(PDF) 39 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU bảng dữ liệu(HTML) 39 Page - SINOWEALTH Electronic Ltd |
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39 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 39 7.8.4 7.8.4 7.8.4 7.8.4 Interrupt Interrupt Interrupt Interrupt Vector Vector Vector Vector When an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is loaded into the program counter. The interrupt vector addresses are listed in Interrupt Interrupt Interrupt Interrupt Summary Summary Summary Summary ttttable able able able. 7.8.5 7.8.5 7.8.5 7.8.5 Interrupt Interrupt Interrupt Interrupt Priority Priority Priority Priority Each interrupt source can be individually programmed to one of four priority levels by setting or clearing corresponding bits in the interrupt priority control registers IPL0, IPH0, IPL1, and IPH1. But the OVL NMI interrupt has the highest Priority Level (except RESET) of all the interrupt sources, with no IPH/IPL control. The interrupt priority service is described below. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but can not by another interrupt with the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which request is serviced. Table Table Table Table 7 7 7 7....30 30 30 30 Interrupt Priority Control Registers Interrupt Interrupt Interrupt Interrupt Priority Priority Priority Priority Priority Priority Priority Priority bits bits bits bits Interrupt Interrupt Interrupt Interrupt Lever Lever Lever Lever Priority Priority Priority Priority IPHx IPLx 0 0 Level 0 (lowest priority) 0 1 Level 1 1 0 Level 2 1 1 Level 3 (highest priority) B8H B8H B8H B8H,,,, B4H B4H B4H B4H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 IPL0 IPL0 IPL0 IPL0 - PADCL - PSL PT1L PX1L PT0L PX0L IPH0 IPH0 IPH0 IPH0 - PADCH - PSH PT1H PX1H PT0H PX0H R/W R/W R/W R/W - R/W - R/W R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) - 0 - 0 0 0 0 0 B9H B9H B9H B9H,,,, B5H B5H B5H B5H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 IPL1 IPL1 IPL1 IPL1 - PFLTL PPWML - PX4L - - - IPH1 IPH1 IPH1 IPH1 - PFLTH PPWMH - PX4H - - - R/W R/W R/W R/W - R/W R/W - R/W - - - Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) - 0 0 - 0 - - - Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description ---- PxxxL/H PxxxL/H PxxxL/H PxxxL/H Corresponding interrupt source xxx’s priority level selection bits |
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