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SH79F024XU bảng dữ liệu(PDF) 67 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU bảng dữ liệu(HTML) 67 Page - SINOWEALTH Electronic Ltd |
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67 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 67 8.3.3 8.3.3 8.3.3 8.3.3 ADC ADC ADC ADC Register Register Register Register Table Table Table Table 8 8 8 8....2 2 2 20 0 0 0 ADC Control Register Note: Note: Note: Note: When select the reference voltage input from VREF pin (REFC = 1), the P0.5 is shared as VREF input rather than AN3 input. Adc sample data from OP out directly, if set SCH as 111. Table Table Table Table 8 8 8 8....2 2 2 21 1 1 1 ADC Channel Configure Register 93H 93H 93H 93H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 ADCON ADCON ADCON ADCON ADON ADCIF EC REFC SCH2 SCH1 SCH0 GO/DONE —---—-----— R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 0 0 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7 7 7 7 AD AD AD ADC C C CON ON ON ON ADC ADC ADC ADC Enable Enable Enable Enable bit bit bit bit 0: Disable the ADC module 1: Enable the ADC module 6 6 6 6 ADCIF ADCIF ADCIF ADCIF ADC ADC ADC ADC Interrupt Interrupt Interrupt Interrupt Flag Flag Flag Flag bit bit bit bit 0: No ADC interrupt, cleared by software. 1: Set by hardware to indicate that the AD Convert has been completed, or analog input is larger than ADDH/ADDL if compare is enabled 5 5 5 5 EC EC EC EC Compare Compare Compare Compare Function Function Function Function Enable Enable Enable Enable bit bit bit bit 0: Compare function disabled 1: Compare function enabled 4 4 4 4 REFC REFC REFC REFC Reference Reference Reference Reference Voltage Voltage Voltage Voltage Select Select Select Select bit bit bit bit 0: the reference voltage connected to VDD 1: the reference voltage input from VREF pin 3-1 3-1 3-1 3-1 SCH[2:0] SCH[2:0] SCH[2:0] SCH[2:0] ADC ADC ADC ADC channel channel channel channel Select Select Select Select bits bits bits bits 000: ADC channel AN0 001: ADC channel AN1 010: ADC channel AN2 011: ADC channel AN3 100: ADC channel AN4 111: OPOUT out put Others: invalid 0 0 0 0 GO/ GO/ GO/ GO/DONE DONE DONE DONE — — — —--- --- --- ---— — — —------ ------ ------ ------— — — — ADC ADC ADC ADC status status status status flag flag flag flag bit bit bit bit 0: Automatically cleared by hardware when AD convert is completed. Clearing this bit during converting time will stop current conversion. If Compare function is enabled, this bit will not be cleared by hardware until software clear. 1: Set to start AD convert or digital compare. 9 9 9 95 5 5 5H H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 ADC ADC ADC ADCH H H H - - - CH4 CH3 CH2 CH1 CH0 R/W R/W R/W R/W - - - R/W R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) - - - 0 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 4 4 4 4-0 -0 -0 -0 CH[ CH[ CH[ CH[4 4 4 4:0] :0] :0] :0] Channel Channel Channel Channel Configuration Configuration Configuration Configuration bits bits bits bits 0: P0.2-P0.6 is I/O port 1: P0.2-P0.6 is ADC input port |
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