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SH79F024XU bảng dữ liệu(PDF) 47 Page - SINOWEALTH Electronic Ltd |
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SH79F024XU bảng dữ liệu(HTML) 47 Page - SINOWEALTH Electronic Ltd |
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47 / 92 page  SH79F SH79F SH79F SH79F082 082 082 082 47 Table Table Table Table 8 8 8 8....9 9 9 9 PWM2/21 Duty Control Register0 (PWM2DL) Table Table Table Table 8 8 8 8....10 10 10 10 PWM2/21 Duty Control Register1 (PWM2DH) Notes: Notes: Notes: Notes: 1. In edge aligned mode, PWM output duty cycle = [PDx.11, PDx.0] X PWM clock. (x = 1, 2) In center aligned mode, PWM output duty cycle = 2 X [PDx.11, PDx.0] X PWM clock. (x = 1, 2) 2. If duty Register = 0x000, no Duty overflow interrupt occurs, but Period overflow interrupt will no be affected. PWM1/2 always outputs inactive level and PWM011/21 always output active level. 3. If Period ≤ Duty, no Duty overflow interrupt occurs, but Period overflow interrupt will no be affected. PWM1/2 always outputs active level and PWM011/21 always output inactive level. 4. When writing these two register, low byte should be written first then write high byte, because high byte writing operation will copy these two register to really counter, only change low byte is useless. 0D2 0D2 0D2 0D2H H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 PWM2DL PWM2DL PWM2DL PWM2DL PD2.7 PD2.6 PD2.5 PD2.4 PD2.3 PD2.2 PD2.1 PD2.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) 0 0 0 0 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 7-0 7-0 7-0 7-0 PD PD PD PD2 2 2 2[7 [7 [7 [7::::0 0 0 0]]]] PWM2/21 duty register low 8 bits 0D3 0D3 0D3 0D3H H H H Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 PWM PWM PWM PWM2 2 2 2DH DH DH DH - - - - PD2.11 PD2.10 PD2.9 PD2.8 R/W R/W R/W R/W - - - - R/W R/W R/W R/W Reset Reset Reset Reset Value Value Value Value ((((POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR POR/WDT/LVR/PIN /PIN /PIN /PIN)))) - - - - 0 0 0 0 Bit Bit Bit Bit Number Number Number Number Bit Bit Bit Bit Mnemonic Mnemonic Mnemonic Mnemonic Description Description Description Description 3-0 3-0 3-0 3-0 PD PD PD PD2[ 2[ 2[ 2[11 11 11 11::::8 8 8 8]]]] PWM2/21 duty register high 4 bits |
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